ASPDAC 2001 - PDF Preprint Papers

ASPDAC 2001 Asia and South Pacific Design Automation Conference

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ASPDAC
2001
ACM

185views Hardware» more ASPDAC 2001»

Power optimization and management in embedded systems

13 years 8 months ago

Download atrak.usc.edu

Power-efficient design requires reducing power dissipation in all parts of the design and during all stages of the design process subject to constraints on the system performance ...

Massoud Pedram

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Id	Views	Title	Status

1	185	Power optimization and management in embedded systems	claim
2	159	Design and implementation of JPEG encoder IP core	claim
3	137	Optimized address assignment for DSPs with SIMD memory accesses	claim
4	130	Area/delay estimation for digital signal processor cores	claim
5	127	High-level design for asynchronous logic	claim
6	126	A new partitioning scheme for improvement of image computation	claim
7	124	Balanced truncation with spectral shaping for RLC interconnects	claim
8	120	Virtual Java/FPGA interface for networked reconfiguration	claim
9	117	Low power techniques for address encoding and memory allocation	claim
10	112	Parameterized MAC unit implementation	claim
11	107	An efficient solution to the storage correspondence problem for large sequential circuits	claim
12	105	Toward better wireload models in the presence of obstacles	claim
13	104	Optimal spacing and capacitance padding for general clock structures	claim
14	104	Processor-programmable memory BIST for bus-connected embedded memories	claim
15	103	Efficient minimum spanning tree construction without Delaunay triangulation	claim
16	102	New graph bipartizations for double-exposure, bright field alternating phase-shift mask layout	claim
17	101	A statistical static timing analysis considering correlations between delays	claim
18	100	Low power implementation of a turbo-decoder on programmable architectures	claim
19	95	Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks	claim
20	95	FAST-SP: a fast algorithm for block placement based on sequence pair	claim
21	94	On speeding up extended finite state machines using catalyst circuitry	claim
22	93	An efficient analytical model of coupled on-chip RLC interconnects	claim
23	91	Device-level placement for analog layout: an opportunity for non-slicing topological representations	claim
24	91	Cell selection from technology libraries for minimizing power	claim
25	90	Hierarchical dummy fill for process uniformity	claim
26	86	Development of PPRAM-link interface (PLIF) IP core for high-speed inter-SoC communication	claim
27	83	Trace-driven system-level power evaluation of system-on-a-chip peripheral cores	claim
28	82	Towards the logic defect diagnosis for partial-scan designs	claim
29	82	Reusable embedded in-circuit emulator	claim
30	82	A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance	claim
31	81	High-level specification and efficient implementation of pipelined circuits	claim
32	81	Low-power high-level synthesis using latches	claim
33	78	Improved crosstalk modeling for noise constrained interconnect optimization	claim
34	78	A new congestion-driven placement algorithm based on cell inflation	claim
35	75	Multi-hit time-to-digital converter VLSI for high-energy physics experiments	claim
36	75	Integrated power supply planning and floorplanning	claim
37	75	Correlation method of circuit-performance and technology fluctuations for improved design reliability	claim
38	73	Synthesis of single-output space compactors with application to scan-based IP cores	claim
39	73	Timed circuits: a new paradigm for high-speed design	claim
40	68	Reducing bus delay in submicron technology using coding	claim
41	59	Module placement with boundary constraints using the sequence-pair representation	claim
42	57	Speech recognition chip for monosyllables	claim

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