ASPDAC 2005 - PDF Preprint Papers

ASPDAC 2005 Asia and South Pacific Design Automation Conference

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ASPDAC
2005
ACM

193views Hardware» more ASPDAC 2005»

VLSI on-chip power/ground network optimization considering decap leakage currents

13 years 10 months ago

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－ In today’s power/ground(P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leak...

Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, ...

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Id	Views	Title	Status

1	193	VLSI on-chip power/ground network optimization considering decap leakage currents	claim
2	158	The polygonal contraction heuristic for rectilinear Steiner tree construction	claim
3	153	Design of clocked circuits using UML	claim
4	149	Leakage control in FPGA routing fabric	claim
5	146	High-level synthesis for DSP applications using heterogeneous functional units	claim
6	142	An AMBA AHB-based reconfigurable SOC architecture using multiplicity of dedicated flyby DMA blocks	claim
7	142	Bridging fault testability of BDD circuits	claim
8	140	A multi-level transmission line network approach for multi-giga hertz clock distribution	claim
9	138	Crowdedness-balanced multilevel partitioning for uniform resource utilization	claim
10	134	Wire congestion and thermal aware 3D global placement	claim
11	133	A novel O(n) parallel banker's algorithm for System-on-a-Chip	claim
12	132	Automatic synthesis and scheduling of multirate DSP algorithms	claim
13	131	Analysis of buffered hybrid structured clock networks	claim
14	130	Sequential equivalence checking using cuts	claim
15	130	Stability analysis of active clock deskewing systems using a control theoretic approach	claim
16	127	Clock network minimization methodology based on incremental placement	claim
17	125	A formalism for functionality preserving system level transformations	claim
18	123	Comparing high-level modeling approaches for embedded system design	claim
19	123	Supporting sequential assumptions in hybrid verification	claim
20	123	Yield driven gate sizing for coupling-noise reduction under uncertainty	claim
21	122	A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines	claim
22	122	Block based statistical timing analysis with extended canonical timing model	claim
23	120	STACCATO: disjoint support decompositions from BDDs through symbolic kernels	claim
24	119	CMP aware shuttle mask floorplanning	claim
25	118	Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction	claim
26	117	Dynamic symmetry-breaking for improved Boolean optimization	claim
27	117	Hierarchical task scheduler for interleaving subtasks on heterogeneous multiprocessor platforms	claim
28	116	A flexible framework for communication evaluation in SoC design	claim
29	116	On combining iteration space tiling with data space tiling for scratch-pad memory systems	claim
30	115	Low-power domino circuits using NMOS pull-up on off-critical paths	claim
31	115	Automatic assume guarantee analysis for assertion-based formal verification	claim
32	114	Redundant-via enhanced maze routing for yield improvement	claim
33	113	Scalable interprocedural register allocation for high level synthesis	claim
34	113	Forward discrete probability propagation method for device performance characterization under process variations	claim
35	111	Fast floorplanning by look-ahead enabled recursive bipartitioning	claim
36	111	Placement with symmetry constraints for analog layout design using TCG-S	claim
37	111	Wave-pipelined on-chip global interconnect	claim
38	110	Compact and stable modeling of partial inductance and reluctance matrices	claim
39	110	An accurate 1.08-GHz CMOS LC voltage-controlled oscillator	claim
40	109	Dynamic power management using on demand paging for networked embedded systems	claim
41	109	Optimal module and voltage assignment for low-power	claim
42	109	BDD-based two variable sharing extraction	claim
43	109	Fault tolerant nanoelectronic processor architectures	claim
44	107	Making fast buffer insertion even faster via approximation techniques	claim
45	107	Constraint extraction for pseudo-functional scan-based delay testing	claim
46	107	Customized on-chip memories for embedded chip multiprocessors	claim
47	107	Substrate resistance extraction with direct boundary element method	claim
48	106	Using loop invariants to fight soft errors in data caches	claim
49	106	On structure and suboptimality in placement	claim
50	105	Interconnect estimation without packing via ACG floorplans	claim
51	104	Speed and voltage selection for GALS systems based on voltage/frequency islands	claim
52	104	Skew scheduling and clock routing for improved tolerance to process variations	claim
53	104	On multiple-voltage high-level synthesis using algorithmic transformations	claim
54	104	Low-power techniques for network security processors	claim
55	103	MAIA: a framework for networks on chip generation and verification	claim
56	102	A framework for automated and optimized ASIP implementation supporting multiple hardware description languages	claim
57	101	Lower bounds for dynamic BDD reordering	claim
58	101	A clustering technique to optimize hardware/software synchronization	claim
59	101	A wideband hierarchical circuit reduction for massively coupled interconnects	claim
60	100	Microarchitecture evaluation with floorplanning and interconnect pipelining	claim
61	99	A fast counterexample minimization approach with refutation analysis and incremental SAT	claim
62	99	Implication of assertion graphs in GSTE	claim
63	98	Bitwidth-aware scheduling and binding in high-level synthesis	claim
64	98	Process variation robust clock tree routing	claim
65	98	Online hardware/software partitioning in networked embedded systems	claim
66	97	Opportunities and challenges for better than worst-case design	claim
67	97	Fast synthesis of exact minimal reversible circuits using group theory	claim
68	96	Comprehensive frequency dependent interconnect extraction and evaluation methodology	claim
69	96	Oscillation ring based interconnect test scheme for SOC	claim
70	95	Timing analysis considering temporal supply voltage fluctuation	claim
71	95	Buffering global interconnects in structured ASIC design	claim
72	94	Probabilistic congestion model considering shielding for crosstalk reduction	claim
73	93	Power minimization for dynamic PLAs	claim
74	92	Detailed placement for improved depth of focus and CD control	claim
75	92	Sleep transistor sizing using timing criticality and temporal currents	claim
76	92	Partitioning and placement for buildable QCA circuits	claim
77	92	An LP-based methodology for improved timing-driven placement	claim
78	91	Efficiently generating test vectors with state pruning	claim
79	91	A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem	claim
80	90	On-chip accumulated jitter measurement for phase-locked loops	claim
81	90	Feasibility analysis of messages for on-chip networks using wormhole routing	claim
82	90	Register placement for low power clock network	claim
83	90	An integrated performance and power model for superscalar processor designs	claim
84	89	Multi-metric and multi-entity characterization of applications for early system design exploration	claim
85	89	System-level design space exploration for security processor prototyping in analytical approaches	claim
86	89	Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction	claim
87	89	Optimal placement by branch-and-price	claim
88	87	Static power minimization in current-mode circuits	claim
89	86	Thermal-driven multilevel routing for 3-D ICs	claim
90	85	Integration of supercubing and learning in a SAT solver	claim
91	84	Design at the end of the silicon roadmap	claim
92	83	Abstracting functionality for modular performance analysis of hard real-time systems	claim
93	82	Return path selection for loop RL extraction	claim
94	81	System-level communication modeling for network-on-chip synthesis	claim
95	81	Standard CMOS technology on-chip inductors with pn junctions substrate isolation	claim
96	81	Power estimation starategies for a low-power security processor	claim
97	81	Design and design automation of rectification logic for engineering change	claim
98	81	Prediction of LC-VCOs' tuning curves with period calculation technique	claim
99	80	Synthesis of quantum logic circuits	claim
100	79	Simulation acceleration of transaction-level models for SoC with RTL sub-blocks	claim
101	79	Floorplan management: incremental placement for gate sizing and buffer insertion	claim
102	78	Timing driven track routing considering coupling capacitance	claim
103	75	Evaluation of the statistical delay quality model	claim
104	74	On-chip thermal gradient analysis and temperature flattening for SoC design	claim
105	73	An-OARSMan: obstacle-avoiding routing tree construction with good length performance	claim
106	72	TERPS: the embedded reliable processing system	claim
107	70	A variation-aware low-power coding methodology for tightly coupled buses	claim
108	65	Library cell layout with Alt-PSM compliance and composability	claim
109	65	Multilevel full-chip gridless routing considering optical proximity correction	claim

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