DAC 1997 - PDF Preprint Papers

DAC 1997 Design Automation Conference

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DAC
1997
ACM

205views Computer Architecture» more DAC 1997»

Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design

13 years 8 months ago

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This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...

Howard H. Chen, David D. Ling

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Id	Views	Title	Status

1	205	Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design	claim
2	205	Static Timing Analysis of Embedded Software	claim
3	205	ATPG for Heat Dissipation Minimization During Scan Testing	claim
4	185	Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT	claim
5	160	Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets	claim
6	156	Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach	claim
7	148	COSYN: Hardware-Software Co-Synthesis of Embedded Systems	claim
8	148	A C-Based RTL Design Verification Methodology for Complex Microprocessor	claim
9	144	Zeros and Passivity of Arnoldi-Reduced-Order Models for Interconnect Networks	claim
10	144	System-Level Synthesis of Low-Power Hard Real-Time Systems	claim
11	140	Methodology for Behavioral Synthesis-Based Algorithm-Level Design Space Exploration: DCT Case Study	claim
12	135	Multilevel Hypergraph Partitioning: Application in VLSI Domain	claim
13	134	CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries	claim
14	132	A Parallel/Serial Trade-Off Methodology for Look-Up Table Based Decoders	claim
15	128	Developing a Concurrent Methodology for Standard-Cell Library Generation	claim
16	128	SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems	claim
17	126	Fast Hardware/Software Co-Simulation for Virtual Prototyping and Trade-Off Analysis	claim
18	126	Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures	claim
19	126	Formal Verification of a Superscalar Execution Unit	claim
20	126	Technology-Dependent Transformations for Low-Power Synthesis	claim
21	123	Toward Formalizing a Validation Methodology Using Simulation Coverage	claim
22	123	Modeling Design Tasks and Tools: The Link Between Product and Flow Model	claim
23	122	SPIE: Sparse Partial Inductance Extraction	claim
24	120	Analytical Estimation of Transition Activity From Word-Level Signal Statistics	claim
25	117	Sequence Compaction for Probabilistic Analysis of Finite-State Machines	claim
26	116	InfoPad - An Experiment in System Level Design and Integration	claim
27	116	System Level Fixed-Point Design Based on an Interpolative Approach	claim
28	114	Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign	claim
29	113	Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits	claim
30	112	Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy	claim
31	112	Remembrance of Things Past: Locality and Memory in BDDs	claim
32	108	CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells	claim
33	108	ISDL: An Instruction Set Description Language for Retargetability	claim
34	107	Optimizing Designs Containing Black Boxes	claim
35	107	Cluster Refinement for Block Placement	claim
36	107	Low Energy Memory and Register Allocation Using Network Flow	claim
37	106	Equivalence Checking Using Cuts and Heaps	claim
38	106	A Graph-Based Synthesis Algorithm for AND/XOR Networks	claim
39	105	Formal Verification of FIRE: A Case Study	claim
40	104	Schedule Validation for Embedded Reactive Real-Time Systems	claim
41	104	Electronic Component Information Exchange (ECIX)	claim
42	104	Power Macromodeling for High Level Power Estimation	claim
43	104	More Practical Bounded-Skew Clock Routing	claim
44	104	Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology	claim
45	104	Structured Design of Microelectromechanical Systems	claim
46	103	Quadratic Placement Revisited	claim
47	103	Tools and Methodologies for Low Power Design	claim
48	103	Safe BDD Minimization Using Don't Cares	claim
49	102	An Improved Algorithm for Minimum-Area Retiming	claim
50	98	High-Level Power Modeling, Estimation, and Optimization	claim
51	96	Hierarchical Sequence Compaction for Power Estimation	claim
52	96	STARBIST: Scan Autocorrelated Random Pattern Generation	claim
53	94	An Efficient Approach to Multi-Layer Layer Assignment with Application to Via Minimization	claim
54	94	Dynamic Communication Models in Embedded System Co-Simulation	claim
55	94	Power Management Techniques for Control-Flow Intensive Designs	claim
56	93	Multilevel Circuit Partitioning	claim
57	93	Optimal Wire-Sizing Function with Fringing Capacitance Consideration	claim
58	93	Post-Layout Logic Restructuring for Performance Optimization	claim
59	92	A Power Estimation Framework for Designing Low Power Portable Video Applications	claim
60	90	Frequency-Domain Compatibility in Digital Filter BIST	claim
61	89	Computer-Aided Design of Free-Space Opto-Electronic Systems	claim
62	89	Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation	claim
63	88	An Integrated Design Environment for Performance and Dependability Analysis	claim
64	86	Preservation of Passivity During RLC Network Reduction via Split Congruence Transformations	claim
65	86	A Hybrid Algorithm for Test Point Selection for Scan-Based BIST	claim
66	82	Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits	claim
67	82	Synthesis of Speed-Independent Circuits from STG-Unfolding Segment	claim
68	80	Profile-Driven Program Synthesis for Evaluation of System Power Dissipation	claim
69	77	An Efficient Implementation of Reactivity for Modeling Hardware in the Scenic Design Environment	claim
70	77	Timing Optimization for Multi-Source Nets: Characterization and Optimal Repeater Insertion	claim
71	75	Wire Segmenting for Improved Buffer Insertion	claim
72	75	A Dynamic Design Estimation and Exploration Environment	claim
73	75	Efficient Testing of Clock Regenerator Circuits in Scan Designs	claim
74	74	Potential-Driven Statistical Ordering of Transformations	claim
75	74	Interface-Based Design	claim
76	64	Formal Verification in a Commercial Setting	claim
77	59	Synthesis of Application Specific Programmable Processors	claim

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