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DAC
2005
ACM

240views Computer Architecture» more DAC 2005»

FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology

14 years 5 months ago

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In this paper, we describe FLEXBUS, a flexible, high-performance onchip communication architecture featuring a dynamically configurable topology. FLEXBUS is designed to detect run...

Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...

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Id	Views	Title	Status

1	240	FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology	claim
2	204	Hardware speech recognition for user interfaces in low cost, low power devices	claim
3	193	Multiplexer restructuring for FPGA implementation cost reduction	claim
4	184	An effective power mode transition technique in MTCMOS circuits	claim
5	176	Power emulation: a new paradigm for power estimation	claim
6	176	Enhanced leakage reduction Technique by gate replacement	claim
7	175	Automatic generation of customized discrete fourier transform IPs	claim
8	171	Asynchronous circuits transient faults sensitivity evaluation	claim
9	169	A new canonical form for fast boolean matching in logic synthesis and verification	claim
10	167	Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions	claim
11	162	An efficient algorithm for statistical minimization of total power under timing yield constraints	claim
12	161	Power-aware placement
13	161	A non-parametric approach for dynamic range estimation of nonlinear systems	claim
14	159	Towards scalable flow and context sensitive pointer analysis	claim
15	156	Designing logic circuits for probabilistic computation in the presence of noise	claim
16	155	Response compaction with any number of unknowns using a new LFSR architecture	claim
17	153	Microarchitecture-aware floorplanning using a statistical design of experiments approach	claim
18	151	Fine-grained application source code profiling for ASIP design	claim
19	151	Mapping statistical process variations toward circuit performance variability: an analytical modeling approach	claim
20	149	Simulation based deadlock analysis for system level designs	claim
21	149	Efficient fingerprint-based user authentication for embedded systems	claim
22	149	FPGA technology mapping: a study of optimality	claim
23	148	Smart diagnostics for configurable processor verification	claim
24	145	Full-chip analysis of leakage power under process variations, including spatial correlations	claim
25	144	VLIW: a case study of parallelism verification	claim
26	142	Matlab as a development environment for FPGA design	claim
27	141	A combined feasibility and performance macromodel for analog circuits	claim
28	141	Cognitive radio techniques for wide area networks	claim
29	140	Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions	claim
30	139	StressTest: an automatic approach to test generation via activity monitors	claim
31	139	How accurately can we model timing in a placement engine?	claim
32	139	A design platform for 90-nm leakage reduction techniques	claim
33	138	A low latency router supporting adaptivity for on-chip interconnects	claim
34	138	Diffusion-based placement migration	claim
35	137	High performance encryption cores for 3G networks	claim
36	135	Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse	claim
37	135	BEOL variability and impact on RC extraction	claim
38	134	Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method	claim
39	134	Robust gate sizing by geometric programming	claim
40	134	Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs	claim
41	133	Efficient SAT solving: beyond supercubes	claim
42	132	Logic soft errors in sub-65nm technologies design and CAD challenges	claim
43	131	MiniBit: bit-width optimization via affine arithmetic	claim
44	130	Improving java virtual machine reliability for memory-constrained embedded systems	claim
45	130	Design methodology for IC manufacturability based on regular logic-bricks	claim
46	130	A green function-based parasitic extraction method for inhomogeneous substrate layers	claim
47	129	Incremental exploration of the combined physical and behavioral design space	claim
48	129	Locality-conscious workload assignment for array-based computations in MPSOC architectures	claim
49	129	Modular domain-specific implementation and exploration framework for embedded software platforms	claim
50	128	A novel synthesis approach for active leakage power reduction using dynamic supply gating	claim
51	128	Minimizing peak current via opposite-phase clock tree	claim
52	127	Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages	claim
53	127	Partitioning-based approach to fast on-chip decap budgeting and minimization	claim
54	127	Are there economic benefits in DFM?	claim
55	126	Minimising buffer requirements of synchronous dataflow graphs with model checking	claim
56	126	Automatic scenario detection for improved WCET estimation	claim
57	126	Energy optimal speed control of devices with discrete speed sets	claim
58	125	Architecture-adaptive range limit windowing for simulated annealing FPGA placement	claim
59	125	IODINE: a tool to automatically infer dynamic invariants for hardware designs	claim
60	125	Simulation models for side-channel information leaks	claim
61	125	Performance space modeling for hierarchical synthesis of analog integrated circuits	claim
62	125	Hybrid simulation for embedded software energy estimation	claim
63	124	A general framework for accurate statistical timing analysis considering correlations	claim
64	124	MP core: algorithm and design techniques for efficient channel estimation in wireless applications	claim
65	124	Efficient and accurate gate sizing with piecewise convex delay models	claim
66	124	Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits	claim
67	123	Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration	claim
68	123	Incremental retiming for FPGA physical synthesis	claim
69	123	A quasi-convex optimization approach to parameterized model order reduction	claim
70	122	Statistical static timing analysis: how simple can we get?	claim
71	122	Race-condition-aware clock skew scheduling	claim
72	122	Normalization at the arithmetic bit level	claim
73	121	Variations-aware low-power design with voltage scaling	claim
74	121	Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility	claim
75	121	Prime clauses for fast enumeration of satisfying assignments to boolean circuits	claim
76	121	N-detection under transparent-scan	claim
77	120	Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design	claim
78	120	System-level energy-efficient dynamic task scheduling	claim
79	120	Exploring technology alternatives for nano-scale FPGA interconnects	claim
80	120	DFM rules!	claim
81	120	Differentiate and deliver: leveraging your partners	claim
82	119	Flexible ASIC: shared masking for multiple media processors	claim
83	119	Piece-wise approximations of RLCK circuit responses using moment matching	claim
84	118	Analysis of full-wave conductor system impedance over substrate using novel integration techniques	claim
85	118	Power optimal dual-Vdd buffered tree considering buffer stations and blockages	claim
86	117	Beyond safety: customized SAT-based model checking	claim
87	117	Dynamic slack reclamation with procrastination scheduling in real-time embedded systems	claim
88	117	Scalable trajectory methods for on-demand analog macromodel extraction	claim
89	117	Circuit optimization using statistical static timing analysis	claim
90	117	Spatially distributed 3D circuit models	claim
91	117	Dynamic abstraction using SAT-based BMC	claim
92	116	A lattice-based framework for the classification and design of asynchronous pipelines	claim
93	116	Power grid simulation via efficient sampling-based sensitivity analysis and hierarchical symbolic relaxation	claim
94	116	Path delay test compaction with process variation tolerance	claim
95	115	Automated nonlinear Macromodelling of output buffers for high-speed digital applications	claim
96	115	Sign bit reduction encoding for low power applications	claim
97	114	Multilevel full-chip routing for the X-based architecture	claim
98	114	Variability and energy awareness: a microarchitecture-level perspective	claim
99	114	Formal verification: is it real enough?	claim
100	114	Multi-frequency wrapper design and optimization for embedded cores under average power constraints	claim
101	113	Systematic development of analog circuit structural macromodels through behavioral model decoupling	claim
102	112	Segregation by primary phase factors: a full-wave algorithm for model order reduction	claim
103	112	OPERA: optimization with ellipsoidal uncertainty for robust analog IC design	claim
104	112	Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model	claim
105	112	TCAM enabled on-chip logic minimization	claim
106	112	An effective DFM strategy requires accurate process and IP pre-characterization	claim
107	111	Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction	claim
108	111	Correlation-aware statistical timing analysis with non-gaussian delay distributions	claim
109	111	Matlab extensions for the development, testing and verification of real-time DSP software	claim
110	110	Multi-threaded reachability	claim
111	110	High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trade-offs	claim
112	110	The Titanic: what went wrong!	claim
113	109	Device and architecture co-optimization for FPGA power reduction	claim
114	109	Low power network processor design using clock gating	claim
115	108	Explaining the gap between ASIC and custom power: a custom perspective	claim
116	107	Effective bounding techniques for solving unate and binate covering problems	claim
117	106	A generic micro-architectural test plan approach for microprocessor verification	claim
118	106	Navigating registers in placement for clock network minimization	claim
119	106	Design methodology for wireless nodes with printed antennas	claim
120	105	Word level predicate abstraction and refinement for verifying RTL verilog	claim
121	104	ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction	claim
122	104	Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips	claim
123	104	Timing-driven placement by grid-warping	claim
124	103	Structural search for RTL with predicate learning	claim
125	103	User-perceived latency driven voltage scaling for interactive applications	claim
126	103	Template-driven parasitic-aware optimization of analog integrated circuit layouts	claim
127	103	Keeping hot chips cool	claim
128	103	Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits	claim
129	102	Floorplan-aware automated synthesis of bus-based communication architectures	claim
130	102	Operator-based model-order reduction of linear periodically time-varying systems	claim
131	102	Structure preserving reduction of frequency-dependent interconnect	claim
132	102	Wireless platforms: GOPS for cents and MilliWatts	claim
133	102	MIMO technology for advanced wireless local area networks	claim
134	101	Exploiting suspected redundancy without proving it	claim
135	100	Approximate VCCs: a new characterization of multimedia workloads for system-level MpSoC design	claim
136	100	On the need for statistical timing analysis	claim
137	99	Net weighting to reduce repeater counts during placement	claim
138	99	Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC	claim
139	99	RF MEMS in wireless architectures	claim
140	97	Optimal procrastinating voltage scheduling for hard real-time systems	claim
141	97	Closing the power gap between ASIC and custom: an ASIC perspective	claim
142	96	Leakage power optimization with dual-Vth library in high-level synthesis	claim
143	96	SEU tolerant device, circuit and processor design	claim
144	95	Frequency-based code placement for embedded multiprocessors	claim
145	95	Mixed signal design space exploration through analog platforms	claim
146	95	A pattern matching coprocessor for network security	claim
147	95	A variation tolerant subthreshold design approach	claim
148	94	Trace-driven HW/SW cosimulation using virtual synchronization technique	claim
149	94	Logic block clustering of large designs for channel-width constrained FPGAs	claim
150	94	Is methodology the highway out of verification hell?	claim
151	94	A unified optimization framework for equalization filter synthesis	claim
152	94	Structured/platform ASIC apprentices: which platform will survive your board room?	claim
153	93	Temperature-aware resource allocation and binding in high-level synthesis	claim
154	93	Secure scan: a design-for-test architecture for crypto chips	claim
155	93	Streamline verification process with formal property verification to meet highly compressed design cycle	claim
156	89	Path based buffer insertion	claim
157	88	From myth to methodology: cross-layer design for energy-efficient wireless communication	claim
158	88	RADAR: RET-aware detailed routing using fast lithography simulations	claim
159	88	An exact jumper insertion algorithm for antenna effect avoidance/fixing	claim
160	88	Deterministic approaches to analog performance space exploration (PSE)	claim
161	87	Implementing low-power configurable processors: practical options and tradeoffs	claim
162	87	Faster and better global placement by a new transportation algorithm	claim
163	87	Variation-tolerant circuits: circuit solutions and techniques	claim
164	85	DTM: dynamic tone mapping for backlight scaling	claim
165	83	A watermarking system for IP protection by a post layout incremental router	claim
166	81	Can we really do without the support of formal methods in the verification of large designs?	claim

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