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DAC
2007
ACM

200views Computer Architecture» more DAC 2007»

NBTI-Aware Synthesis of Digital Circuits

14 years 5 months ago

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Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatneka...

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Id	Views	Title	Status

1	200	NBTI-Aware Synthesis of Digital Circuits	claim
2	200	Hardware Support for Secure Processing in Embedded Systems	claim
3	196	Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors	claim
4	192	A Self-Tuning Configurable Cache	claim
5	190	Automotive Software Integration	claim
6	185	Endurance Enhancement of Flash-Memory Storage, Systems: An Efficient Static Wear Leveling Design	claim
7	180	Physical Unclonable Functions for Device Authentication and Secret Key Generation	claim
8	178	SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits	claim
9	172	Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations	claim
10	172	Verification Methodologies in a TLM-to-RTL Design Flow	claim
11	168	Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis	claim
12	164	Synthetic biology: from bacteria to stem cells	claim
13	160	Implicitly Parallel Programming Models for Thousand-Core Microprocessors	claim
14	160	Side-Channel Attack Pitfalls	claim
15	155	Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction	claim
16	155	Modeling the Function Cache for Worst-Case Execution Time Analysis	claim
17	155	Parameterized Macromodeling for Analog System-Level Design Exploration	claim
18	154	Optimization of Area in Digital FIR Filters using Gate-Level Metrics	claim
19	154	Program Mapping onto Network Processors by Recursive Bipartitioning and Refining	claim
20	154	Gate Sizing For Cell Library-Based Designs	claim
21	153	Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification	claim
22	153	Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip	claim
23	152	Global Critical Path: A Tool for System-Level Timing Analysis	claim
24	152	Automatic Verification of External Interrupt Behaviors for Microprocessor Design	claim
25	151	Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement	claim
26	150	Chip Multi-Processor Generator	claim
27	149	DDBDD: Delay-Driven BDD Synthesis for FPGAs	claim
28	148	CAD Implications of New Interconnect Technologies	claim
29	146	Dynamic Power Management with Hybrid Power Sources	claim
30	146	Trusted Hardware: Can It Be Trustworthy?	claim
31	145	The KILL Rule for Multicore	claim
32	143	A System For Coarse Grained Memory Protection In Tiny Embedded Processors	claim
33	143	Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits	claim
34	143	An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design	claim
35	142	Placement of 3D ICs with Thermal and Interlayer Via Considerations	claim
36	141	Design Methodology for Pipelined Heterogeneous Multiprocessor System	claim
37	141	Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications	claim
38	140	Alembic: An Efficient Algorithm for CNF Preprocessing	claim
39	138	Memory Modeling in ESL-RTL Equivalence Checking	claim
40	137	Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting	claim
41	137	Compact State Machines for High Performance Pattern Matching	claim
42	136	Energy-Aware Data Compression for Multi-Level Cell (MLC) Flash Memory	claim
43	135	Novel CNTFET-based Reconfigurable Logic Gate Design	claim
44	135	Programming Living Cells to Function as Massively Parallel Computers	claim
45	134	Synthesizing Stochasticity in Biochemical Systems	claim
46	133	PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels	claim
47	131	Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop	claim
48	130	IPR: An Integrated Placement and Routing Algorithm	claim
49	130	A New Twisted Differential Line Structure in Global Bus Design	claim
50	129	Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits	claim
51	128	Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies	claim
52	127	GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches	claim
53	127	Parameter Finding Methods for Oscillators with a Specified Oscillation Frequency	claim
54	127	Multi-Core Design Automation Challenges	claim
55	127	Performance Analysis of FlexRay-based ECU Networks	claim
56	126	Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design	claim
57	125	An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration	claim
58	125	Modeling Safe Operating Area in Hardware Description Languages	claim
59	124	Scan Test Planning for Power Reduction	claim
60	124	RISPP: Rotating Instruction Set Processing Platform	claim
61	123	Shared Resource Access Attributes for High-Level Contention Models	claim
62	123	TLM: Crossing Over From Buzz To Adoption	claim
63	122	Fast Min-Cost Buffer Insertion under Process Variations	claim
64	121	Synchronous Elastic Circuits with Early Evaluation and Token Counterflow	claim
65	120	Effects of Coupling Capacitance and Inductance on Delay Uncertainty and Clock Skew	claim
66	118	SODA: Sensitivity Based Optimization of Disk Architecture	claim
67	118	Analog Placement Based on Novel Symmetry-Island Formulation	claim
68	117	Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors	claim
69	117	Computationally Efficient Power Integrity Simulation for System-on-Package Applications	claim
70	116	Optimal Selection of Voltage Regulator Modules in a Power Delivery Network	claim
71	116	Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs	claim
72	116	MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs	claim
73	115	Layered Switching for Networks on Chip	claim
74	115	On-The-Fly Resolve Trace Minimization	claim
75	115	Design for Verification in System-level Models and RTL	claim
76	114	Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization	claim
77	113	Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation	claim
78	113	A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices	claim
79	112	Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage	claim
80	112	Period Optimization for Hard Real-time Distributed Automotive Systems	claim
81	112	High Performance and Low Power Electronics on Flexible Substrate	claim
82	111	Enhancing FPGA Performance for Arithmetic Circuits	claim
83	111	Reliability Analysis for Flexible Electronics: Case Study of Integrated a-Si: H TFT Scan Driver	claim
84	111	Integrated Droplet Routing in the Synthesis of Microfluidic Biochips	claim
85	111	A Framework for the Validation of Processor Architecture Compliance	claim
86	111	Statistical Framework for Technology-Model-Product Co-Design and Convergence	claim
87	111	Trusted Design in FPGAs	claim
88	110	An Effective Guidance Strategy for Abstraction-Guided Simulation	claim
89	110	On Resolution Proofs for Combinational Equivalence	claim
90	106	The Case for Low-Power Photonic Networks on Chip	claim
91	106	Nanometer Device Scaling in Subthreshold Circuits	claim
92	105	Experimental Jitter Analysis in a FlexCAN Based Drive-by-Wire Automotive Application	claim
93	104	Topology-Based Optimization of Maximal Sustainable Throughput in a Latency-Insensitive System	claim
94	102	Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits	claim
95	100	TROY: Track Router with Yield-driven Wire Planning	claim
96	100	An Efficient Mechanism for Performance Optimization of Variable-Latency Designs	claim
97	100	Functional Verification of SiCortex Multiprocessor System-on-a-Chip	claim
98	99	SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects	claim
99	98	Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design	claim
100	97	Efficient Computation of Buffer Capacities for Cyclo-Static Dataflow Graphs	claim
101	96	Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits	claim
102	95	Reducing Data-Memory Footprint of Multimedia Applications by Delay Redistribution	claim
103	91	Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift	claim
104	91	Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits	claim
105	88	Self-Resetting Latches for Asynchronous Micro-Pipelines	claim
106	85	The Case for the Precision Timed (PRET) Machine	claim
107	82	RQL: Global Placement via Relaxed Quadratic Spreading and Linearization	claim

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