DAC 2012 - PDF Preprint Papers

DAC 2012 Design Automation Conference

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DAC
2012
ACM

350views Computer Architecture» more DAC 2012»

Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse

11 years 6 months ago

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Due to the breakdown of Dennardian scaling, the percentage of a silicon chip that can switch at full frequency is dropping exponentially with each process generation. This utiliza...

Michael B. Taylor

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Id	Views	Title	Status

1	350	Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse	claim
2	294	Chisel: constructing hardware in a Scala embedded language	claim
3	244	ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement	claim
4	235	Assessing the performance limits of parallelized near-threshold computing	claim
5	231	On software design for stochastic processors	claim
6	228	Equivalence checking for behaviorally synthesized pipelines	claim
7	226	Run-time power-down strategies for real-time SDRAM memory controllers	claim
8	222	GDRouter: interleaved global routing and detailed routing for ultimate routability	claim
9	221	Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs	claim
10	221	Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI	claim
11	221	An information-theoretic framework for optimal temperature sensor allocation and full-chip thermal monitoring	claim
12	216	A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC	claim
13	210	Process variation in near-threshold wide SIMD architectures	claim
14	210	Statistical design and optimization for adaptive post-silicon tuning of MEMS filters	claim
15	207	Self-aware computing in the Angstrom processor	claim
16	205	Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs	claim
17	201	Towards fault-tolerant embedded systems with imperfect fault detection	claim
18	198	WCET-centric partial instruction cache locking	claim
19	197	Improving gate-level simulation accuracy when unknowns exist	claim
20	197	High radix self-arbitrating switch fabric with multiple arbitration schemes and quality of service	claim
21	192	Exploiting die-to-die thermal coupling in 3D IC placement	claim
22	181	STM concurrency control for embedded real-time software with tighter time bounds	claim
23	175	A metric for layout-friendly microarchitecture optimization in high-level synthesis	claim
24	174	Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs	claim

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