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DATE
2004
IEEE

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Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow

13 years 8 months ago

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Emerging embedded system applications in multimedia and image processing are characterized by complex control flow consisting of deeply nested conditionals and loops. We present a...

Sumit Gupta, Nikil Dutt, Rajesh Gupta, Alexandru N...

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Id	Views	Title	Status

1	210	Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow	claim
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9	173	Supporting Cache Coherence in Heterogeneous Multiprocessor Systems	claim
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51	134	Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding	claim
52	134	Arithmetic Reasoning in DPLL-Based SAT Solving	claim
53	134	Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor	claim
54	133	Channel Decoder Architecture for 3G Mobile Wireless Terminals	claim
55	133	Model-Based Specification and Execution of Embedded Real-Time Systems	claim
56	132	LZW-Based Code Compression for VLIW Embedded Systems	claim
57	132	Hybrid Architectural Dynamic Thermal Management	claim
58	131	Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures	claim
59	131	Testing of Quantum Dot Cellular Automata Based Designs	claim
60	130	Dynamic Power Management Using Data Buffers	claim
61	130	Utilizing Formal Assertions for System Design of Network Processors	claim
62	130	Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology	claim
63	130	Thermal and Power Integrity Based Power/Ground Networks Optimization	claim
64	129	Improving Design and Verification Productivity with VHDL-200x	claim
65	129	Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach	claim
66	129	On the Design and Verification Methodology of the Look-Aside Interface	claim
67	129	Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach	claim
68	128	Enhanced Diameter Bounding via Structural	claim
69	128	A Crosstalk Aware Interconnect with Variable Cycle Transmission	claim
70	128	An Assembler Driven Verification Methodology (ADVM)	claim
71	128	Synthesis for Manufacturability: A Sanity Check	claim
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77	125	Extremely Low-Power Logic	claim
78	125	Local Decisions and Triggering Mechanisms for Adaptive Fault-Tolerance	claim
79	123	On Concurrent Error Detection with Bounded Latency in FSMs	claim
80	123	Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies	claim
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82	121	Experiences during the Experimental Validation of the Time-Triggered Architecture	claim
83	121	Overhead-Free Polymorphism in Network-on-Chip Implementation of Object-Oriented Models	claim
84	120	Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study	claim
85	120	Direct Nonlinear Order Reduction with Variational Analysis	claim
86	120	Pattern Selection for Testing of Deep Sub-Micron Timing Defects	claim
87	120	Evaluation of SystemC Modelling of Reconfigurable Embedded Systems	claim
88	119	Configuration-Sensitive Process Scheduling for FPGA-Based Computing Platforms	claim
89	119	MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor	claim
90	119	Net and Pin Distribution for 3D Package Global Routing	claim
91	119	Using a Victim Buffer in an Application-Specific Memory Hierarchy	claim
92	118	Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals	claim
93	118	SCORE: SPICE COmpatible Reluctance Extraction	claim
94	118	Distributed Multimedia System Design: A Holistic Perspective	claim
95	117	Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks	claim
96	116	OCCN: A Network-On-Chip Modeling and Simulation Framework	claim
97	116	A Novel SAT All-Solutions Solver for Efficient Preimage Computation	claim
98	116	Full-Chip Multilevel Routing for Power and Signal Integrity	claim
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100	114	Synthesis of Reversible Logic	claim
101	114	Scheduling Reusable Instructions for Power Reduction	claim
102	114	Workload Characterization Model for Tasks with Variable Execution Demand	claim
103	114	Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks	claim
104	113	Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications	claim
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107	110	Interactive Cosimulation with Partial Evaluation	claim
108	109	Using Counter Example Guided Abstraction Refinement to Find Complex Bugs	claim
109	109	RTL Processor Synthesis for Architecture Exploration and Implementation	claim
110	108	Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures	claim
111	108	Poor Man's TBR: A Simple Model Reduction Scheme	claim
112	107	A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms	claim
113	107	Profile Guided Management of Code Partitions for Embedded Systems	claim
114	106	Realizable Reduction for Electromagnetically Coupled RLMC Interconnects	claim
115	106	A Self-Tuning Cache Architecture for Embedded Systems	claim
116	105	Time-Energy Design Space Exploration for Multi-Layer Memory Architectures	claim
117	103	A Novel Implementation of Tile-Based Address Mapping	claim
118	102	High Security Smartcards	claim
119	97	A Formal Verification Methodology for Checking Data Integrity	claim
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123	80	Random Jitter Extraction Technique in a Multi-Gigahertz Signal	claim
124	79	Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits	claim

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