Sciweavers

Share
DDECS   2009 Design and Diagnostics of Electronic Circuits and Systems
Wall of Fame | Most Viewed DDECS-2009 Paper
DDECS
2009
IEEE
202views Hardware» more  DDECS 2009»
8 years 11 months ago
Asynchronous two-level logic of reduced cost
— We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints....
Igor Lemberski, Petr Fiser
Disclaimer and Copyright Notice
Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.
IdReadViewsTitleStatus
1Download preprint from source202
2Download preprint from source171
3Download preprint from source149
4Download preprint from source146
5Download preprint from source129
6Download preprint from source128
7Download preprint from source116
8Download preprint from source111
9Download preprint from source107
10Download preprint from source106
11Download preprint from source95
books