DSD 2007 - PDF Preprint Papers

DSD 2007 Euromicro Symposium on Digital Systems Design

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DSD
2007
IEEE

217views Hardware» more DSD 2007»

Component-Based Hardware/Software Co-Simulation

13 years 10 months ago

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Developing highly efﬁcient and reliable embedded systems demands hardware/software (HW/SW) co-design and, therefore, co-simulation. In order to be highly conﬁgurable, embedded...

Ping Hang Cheung, Kecheng Hao, Fei Xie

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Id	Views	Title	Status

1	217	Component-Based Hardware/Software Co-Simulation	claim
2	178	An Efficient Intra Prediction Hardware Architecture for H.264 Video Decoding	claim
3	164	An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation	claim
4	164	Execution-time Prediction for Dynamic Streaming Applications with Task-level Parallelism	claim
5	163	Architecture of a Small Low-Cost Satellite	claim
6	160	Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays	claim
7	151	P-Ware: A precise and scalable component-based simulation tool for embedded multiprocessor industrial applications	claim
8	150	Adaptive Distance Estimation and Localization in WSN using RSSI Measures	claim
9	142	Decoupling of Computation and Communication with a Communication Assist	claim
10	140	Pseudo-Random Pattern Generator Design for Column-Matching BIST	claim
11	136	Error-Aware Design	claim
12	133	A Serial Logarithmic Number System ALU	claim
13	132	On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology	claim
14	131	Design and Implementation of a 50MHZ DXT CoProcessor	claim
15	122	Energy Based Design Space Exploration of Multiprocessor VLIW Architectures	claim
16	120	Latency Minimization for Synchronous Data Flow Graphs	claim
17	120	Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction	claim
18	119	Online Protocol Testing for FPGA Based Fault Tolerant Systems	claim
19	117	On Complexity of Internal and External Equivalence Checking	claim
20	116	Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation	claim
21	116	Evaluating the Model Accuracy in Automated Design Space Exploration	claim
22	114	General Digit-Serial Normal Basis Multiplier with Distributed Overlap	claim
23	110	Proving Completeness of Properties in Formal Verification of Counting Heads for Railways	claim
24	105	Scaling Analytical Models for Soft Error Rate Estimation Under a Multiple-Fault Environment	claim
25	98	Fault Diagnosis in Integrated Circuits with BIST	claim
26	96	Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties	claim
27	91	Increasing NoC Performance and Utilisation using a Dual Packet Exit Strategy	claim
28	88	An Implementation of an Address Generator Using Hash Memories	claim
29	87	On the Construction of Small Fully Testable Circuits with Low Depth	claim
30	86	Toggle Equivalence Preserving (TEP) Logic Optimization	claim
31	86	On network-on-chip comparison	claim
32	83	Hierarchical Identification of Untestable Faults in Sequential Circuits	claim
33	75	Novel Agent-Based Management for Fault-Tolerance in Network-on-Chip	claim

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