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ERSA
2006

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SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture

13 years 5 months ago

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Reconfigurable devices, such as FPGAs, introduce into the design workflow of embedded systems a new degree of freedom: the designer can have the system autonomously modify the fun...

Carlo Amicucci, Fabrizio Ferrandi, Marco D. Santam...

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Id	Views	Title	Status

1	282	SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture	claim
2	197	A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning System	claim
3	186	The Case for High Level Programming Models for Reconfigurable Computers	claim
4	161	A Parametric Study of Scalable Interconnects on FPGAs	claim
5	150	An Area Time Efficient Field Programmable Mersenne Twister Uniform Random Number Generator	claim
6	147	Code Partitioning for Reconfigurable High-Performance Computing: A Case Study	claim
7	133	An FPGA based Co-Design Architecture for MIMO Lattice Decoders	claim
8	132	Combinatorial Optimization in Mapping Generalized Template Matching onto Reconfigurable Computers	claim
9	129	Group-Alignment based Accurate Floating-Point Summation on FPGAs	claim
10	128	Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium Architecture	claim
11	124	RTOS-Based Hardware Software Communications and Configuration Management in the Context of a Smart Camera	claim
12	119	Exploiting Hierarchical Configuration to Improve Run-Time MPSoC Task Assignment	claim
13	115	Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation	claim
14	114	Architectural Support for Runtime 2D Partial Reconfiguration	claim
15	113	A Sensor Distribution Algorithm for FPGAs with Minimal Dynamic Reconfiguration Overhead	claim
16	113	Efficient FPGA-based Implementations of the MIMO-OFDM Physical Layer	claim
17	111	Promises and Pitfalls of Reconfigurable Supercomputing	claim
18	109	Synthesis of Object Oriented Models on Reconfigurable Hardware	claim
19	105	A Column Arrangement Algorithm for a Coarse-grained Reconfigurable Architecture	claim
20	102	Process Isolation for Reconfigurable Hardware	claim
21	100	Relocation and Defragmentation for Heterogeneous Reconfigurable Systems	claim
22	99	Low Power Programmable FIR Filtering IP Cores Targeting System-on-a-Reprogrammable-Chip (SoRC)	claim
23	98	Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array	claim
24	98	Hydra: An Energy-efficient and Reconfigurable Network Interface	claim
25	92	The Reinvention of the Microprocessor	claim
26	91	Intrinsic Embedded Hardware Evolution of Block-based Neural Networks	claim
27	89	Multi-Mode Operator for SHA-2 Hash Functions	claim
28	86	GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs	claim
29	82	Cache Architectures for Reconfigurable Hardware	claim
30	82	A Dual Configuration BIST-Based Modular Diagnostic Methodology for Embedded Cores in FPGAs	claim
31	79	Searching RC5-Keys with Distributed Reconfigurable Computing	claim
32	79	Using configurable processors for high-efficiency multiple-processor systems	claim
33	76	Logic Synthesis and Place-and-Route Environment for ORGAs	claim
34	70	Differential Reconfiguration Architecture suitable for a Holographic Memory	claim

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