ERSA 2010 - PDF Preprint Papers

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ERSA
2010

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DAPR: Design Automation for Partially Reconfigurable FPGAs

1 years 3 months ago

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Partial reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requirements...

Shaon Yousuf, Ann Gordon-Ross

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Id	Views	Title	Status
1	84	DAPR: Design Automation for Partially Reconfigurable FPGAs	claim
2	83	An Open Source Circuit Library with Benchmarking Facilities	claim
3	72	FPGA for Computing the Pixel Purity Index Algorithm on Hyperspectral Images	claim
4	67	Reconfigurable Sparse Matrix-Vector Multiplication on FPGAs	claim
5	64	A Self-Reconfigurable Lightweight Interconnect for Scalable Processor Fabrics	claim
6	63	Integrating Application Specification and Performance Prediction for Strategic Design-Space Exploration	claim
7	61	VAPRES: A Customizable and Flexible Base Architecture for Partially Reconfigurable Systems	claim
8	60	Acceleration of FPGA Fault Injection Through Multi-Bit Testing	claim
9	55	Persistent CAD for in-the-field Power Optimization	claim
10	47	Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware	claim
11	46	An Automated Scheduling and Partitioning Algorithm for Scalable Reconfigurable Computing Systems	claim
12	38	Performance Visualization and Exploration for Reconfigurable Computing Applications	claim

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