EURODAC 1994 - PDF Preprint Papers

EURODAC 1994 European Design Automation Conference with EURO-VHDL

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EURODAC
1994
IEEE

377views VHDL» more EURODAC 1994»

VHDL switch level fault simulation

13 years 8 months ago

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Christopher A. Ryan, Joseph G. Tront

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Id	Views	Title	Status

1	377	VHDL switch level fault simulation	claim
2	272	A transformation for integrating VHDL behavioral specification with synthesis and software generation	claim
3	221	Implementation of a SDH STM-N IC for B-ISDN using VHDL based synthesis tools	claim
4	211	Advanced simulation and modeling techniques for hardware quality verification of digital systems	claim
5	209	MOS VLSI circuit simulation by hardware accelerator using semi-natural models	claim
6	186	Algorithms for a switch module routing problem	claim
7	163	VHDL and cyclic corrector codes	claim
8	159	Formal verification of behavioral VHDL specifications: a case study	claim
9	149	A Graphical Approach to Analogue Behavioural Modelling	claim
10	149	A flexible access control mechanism for CAD frameworks	claim
11	148	BiTeS: a BDD based test pattern generator for strong robust path delay faults	claim
12	148	Design automation of self checking circuits	claim
13	148	System-Level Modeling and Verification: a Comprehensive Design Methodology	claim
14	146	Efficient algorithms for interface timing verification	claim
15	145	Testability analysis and improvement from VHDL behavioral specifications	claim
16	141	Exact path sensitization in timing analysis	claim
17	140	GSA: scheduling and allocation using genetic algorithm	claim
18	139	OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming	claim
19	138	A VHDL-based bus model for multi-PCB system design	claim
20	133	Mixed electrical-thermal and electrical-mechanical simulation of electromechatronic systems using PSpice	claim
21	130	Modeling shared variables in VHDL	claim
22	130	RESIST: a recursive test pattern generation algorithm for path delay faults	claim
23	129	Synthesis of Self-Testable Controllers	claim
24	129	Distributed simulation for structural VHDL netlists	claim
25	129	A general state graph transformation framework for asynchronous synthesis	claim
26	129	A portable and extendible testbed for distributed logic simulation	claim
27	128	A component selection algorithm for high-performance pipelines	claim
28	127	A Generalized Signal Transition Graph Model for Specification of Complex Interfaces	claim
29	127	A process algebra interpretation of a verification oriented overlanguage of VHDL	claim
30	127	Optimal equivalent circuits for interconnect delay calculations using moments	claim
31	124	Parallel controller synthesis from a Petri net specification	claim
32	124	Automotive databus simulation using VHDL	claim
33	123	Testing redundant asynchronous circuits by variable phase splitting	claim
34	122	Compiled-code-based simulation with timing verification	claim
35	120	Generating compilers for generated datapaths	claim
36	120	Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay	claim
37	119	Multilevel generalization of relaxation algorithms for circuit simulation	claim
38	118	The semantics of behavioral VHDL '93 descriptions	claim
39	118	A new knowledge-based design manager assistant for CAD frameworks	claim
40	117	Logic and Fault Simulation by Cellular Automata	claim
41	117	Hardware-software-codesign of application specific microcontrollers with the ASM environment	claim
42	117	A hardware environment for prototyping and partitioning based on multiple FPGAs	claim
43	117	Using C to write portable CMOS VLSI module generators	claim
44	117	Parallel algorithms for the simulation of lossy transmission lines	claim
45	117	Generating VHDL models from natural language descriptions	claim
46	116	A performance evaluator for parameterized ASIC architectures	claim
47	115	Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path	claim
48	115	Overall thermal simulation of electronic equipment	claim
49	115	A tightly coupled approach to design and data management	claim
50	115	A method for partitioning UNITY language in hardware and software	claim
51	113	Formal verification of pipeline conflicts in RISC processors	claim
52	112	Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions	claim
53	112	The use of semantic information for control of a complex routing tool	claim
54	110	Symbolic exploration of large circuits with enhanced forward/backward traversals	claim
55	110	An experimental analysis of the effectiveness of the circular self-test path technique	claim
56	109	Fast OFDD based minimization of fixed polarity Reed-Muller expressions	claim
57	106	Scheduling with Environmental Constraints based on Automata Representations	claim
58	105	On Design Rule Correct Maze Routing	claim
59	104	An efficient verification algorithm for parallel controllers	claim
60	94	A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT	claim

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