FPGA 2004 - PDF Preprint Papers

FPGA 2004 International ACM Symposium on Field-Programmable Gate Arrays

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FPGA
2004
ACM

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An embedded true random number generator for FPGAs

13 years 8 months ago

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Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. Until recently, designers using FPGAs had le...

Paul Kohlbrenner, Kris Gaj

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Id	Views	Title	Status

1	234	An embedded true random number generator for FPGAs	claim
2	180	A VHDL MPEG-7 shape descriptor extractor	claim
3	174	A compiled accelerator for biological cell signaling simulations	claim
4	163	Time and area efficient pattern matching on FPGAs	claim
5	158	A novel coarse-grain reconfigurable data-path for accelerating DSP kernels	claim
6	147	The SFRA: a corner-turn FPGA architecture	claim
7	145	Exploration of pipelined FPGA interconnect structures	claim
8	140	Using reconfigurability to achieve real-time profiling for hardware/software codesign	claim
9	137	Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report	claim
10	137	Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources	claim
11	136	Active leakage power optimization for FPGAs	claim
12	133	FPGAs vs. CPUs: trends in peak floating-point performance	claim
13	128	Incremental physical resynthesis for timing optimization	claim
14	126	A synthesis oriented omniscient manual editor	claim
15	121	Application-specific instruction generation for configurable processor architectures	claim
16	121	Divide and concatenate: a scalable hardware architecture for universal MAC	claim
17	121	Highly pipelined asynchronous FPGAs	claim
18	120	Flexibility measurement of domain-specific reconfigurable hardware	claim
19	119	FPGA-based implementation of single-precision exponential unit	claim
20	119	A quantitative analysis of the speedup factors of FPGAs over processors	claim
21	119	In-system FPGA prototyping of an itanium microarchitecture	claim
22	118	Nanowire-based sublithographic programmable logic arrays	claim
23	117	A magnetoelectronic macrocell employing reconfigurable threshold logic	claim
24	116	Low-power technology mapping for FPGA architectures with dual supply voltages	claim
25	107	An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm	claim
26	101	SPFD-based one-to-many rewiring	claim
27	98	Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics	claim
28	81	Reducing leakage energy in FPGAs using region-constrained placement	claim

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