FPGA 2008 - PDF Preprint Papers

FPGA 2008 International ACM Symposium on Field-Programmable Gate Arrays

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FPGA
2008
ACM

623views FPGA» more FPGA 2008»

From the bitstream to the netlist

13 years 5 months ago

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We present an in-depth analysis of the Xilinx bitstream format. The information gathered in this paper allows bitstream compilation and decompilation. While not actually compromis...

Jean-Baptiste Note, Éric Rannaud

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Id	Views	Title	Status

1	623	From the bitstream to the netlist	claim
2	308	Fpga-based data acquisition system for a positron emission tomography (PET) scanner	claim
3	203	Area and delay trade-offs in the circuit and architecture design of FPGAs	claim
4	191	A hardware framework for the fast generation of multiple long-period random number streams	claim
5	184	Mapping for better than worst-case delays in LUT-based FPGA designs	claim
6	174	When FPGAs are better at floating-point than microprocessors	claim
7	174	Pattern-based behavior synthesis for FPGA resource reduction	claim
8	173	The amorphous FPGA architecture	claim
9	170	Architecture-specific packing for virtex-5 FPGAs	claim
10	168	Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs	claim
11	163	TORCH: a design tool for routing channel segmentation in FPGAs	claim
12	163	High-quality, deterministic parallel placement for FPGAs on commodity hardware	claim
13	161	Implementing high-speed string matching hardware for network intrusion detection systems	claim
14	155	A novel FPGA logic block for improved arithmetic performance	claim
15	151	Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs	claim
16	146	FPGA-optimised high-quality uniform random number generators	claim
17	145	FPGA interconnect design using logical effort	claim
18	142	Modeling routing demand for early-stage FPGA architecture development	claim
19	136	A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs	claim
20	136	HybridOS: runtime support for reconfigurable accelerators	claim
21	133	Vector processing as a soft-core CPU accelerator	claim
22	131	WireMap: FPGA technology mapping for improved routability	claim
23	129	Efficient ASIP design for configurable processors with fine-grained resource sharing	claim

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