FPGA 2009 - PDF Preprint Papers

FPGA 2009 International ACM Symposium on Field-Programmable Gate Arrays

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed FPGA-2009 Paper

click to vote

FPGA
2009
ACM

482views FPGA» more FPGA 2009»

A 17ps time-to-digital converter implemented in 65nm FPGA technology

13 years 9 months ago

Download stinfwww.informatik.uni-leipzig.de

This paper presents a new architecture for time-to-digital conversion enabling a time resolution of 17ps over a range of 50ns with a conversion rate of 20MS/s. The proposed archit...

Claudio Favi, Edoardo Charbon

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	482	A 17ps time-to-digital converter implemented in 65nm FPGA technology	claim
2	343	Fpga-based face detection system using Haar classifiers	claim
3	328	Diagonal tracks in FPGAs: a performance evaluation	claim
4	285	PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions	claim
5	273	A parallel/vectorized double-precision exponential core to accelerate computational science applications	claim
6	260	Fast and scalable packet classification using perfect hash functions	claim
7	233	FPCNA: a field programmable carbon nanotube array	claim
8	209	SPR: an architecture-adaptive CGRA mapping tool	claim
9	201	A high-performance FPGA architecture for restricted boltzmann machines	claim
10	200	FPGA-based front-end electronics for positron emission tomography	claim
11	196	Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs	claim
12	188	Clock power reduction for virtex-5 FPGAs	claim
13	183	A comparison of via-programmable gate array logic cell circuits	claim
14	183	HW/SW methodologies for synchronization in FPGA multiprocessors	claim
15	180	Scalable don't-care-based logic optimization and resynthesis	claim
16	180	CMOS vs Nano: comrades or rivals?	claim
17	168	Large-scale wire-speed packet classification on FPGAs	claim
18	159	Choose-your-own-adventure routing: lightweight load-time defect avoidance	claim
19	154	Synthesis of reconfigurable high-performance multicore systems	claim
20	151	Wirelength modeling for homogeneous and heterogeneous FPGA architectural development	claim
21	150	Bus mastering PCI express in an FPGA	claim
22	148	SmartOpt: an industrial strength framework for logic synthesis	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers