FPL 2004 - PDF Preprint Papers

FPL 2004 International Conference on Field Programmable Logic and Applications

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FPL
2004
Springer

205views Hardware» more FPL 2004»

A System Level Resource Estimation Tool for FPGAs

13 years 9 months ago

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Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...

Changchun Shi, James Hwang, Scott McMillan, Ann Ro...

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Id	Views	Title	Status

1	205	A System Level Resource Estimation Tool for FPGAs	claim
2	171	A Modular System for FPGA-Based TCP Flow Processing in High-Speed Networks	claim
3	164	Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors	claim
4	154	High Performance True Random Number Generator in Altera Stratix FPLDs	claim
5	147	Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs	claim
6	144	A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms	claim
7	143	Exploring Area/Delay Tradeoffs in an AES FPGA Implementation	claim
8	142	IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter	claim
9	141	Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs	claim
10	130	BIST Based Interconnect Fault Location for FPGAs	claim
11	128	Design and Implementation of a CFAR Processor for Target Detection	claim
12	125	SoftSONIC: A Customisable Modular Platform for Video Applications	claim
13	122	Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path	claim
14	119	Reconfigurable Instruction Set Extension for Enabling ECC on an 8-Bit Processor	claim
15	117	Flow Monitoring in High-Speed Networks with 2D Hash Tables	claim
16	115	Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices	claim
17	114	Artificial Neural Networks Processor - A Hardware Implementation Using a FPGA	claim
18	113	An Evolvable Hardware Tutorial	claim
19	112	Storage Allocation for Diverse FPGA Memory Specifications	claim
20	112	Automating the Layout of Reconfigurable Subsystems via Template Reduction	claim
21	110	Versatile Imaging Architecture Based on a System on Chip	claim
22	109	Hardware Accelerated Novel Protein Identification	claim
23	106	FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications	claim
24	105	FPGA Acceleration of Rigid Molecule Interactions	claim
25	103	Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs	claim
26	103	JHDLBits: The Merging of Two Worlds	claim
27	101	The Chess Monster Hydra	claim
28	101	Automatic Creation of Reconfigurable PALs/PLAs for SoC	claim
29	100	On Optimal Irregular Switch Box Designs	claim
30	99	A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development	claim
31	98	Power-Driven Design Partitioning	claim
32	95	Improving FPGA Performance and Area Using an Adaptive Logic Module	claim
33	95	Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor	claim
34	95	Increasing Pipelined IP Core Utilization in Process Networks Using Exploration	claim
35	94	Evaluating Fault Emulation on FPGA	claim
36	93	Second Order Function Approximation Using a Single Multiplication on FPGAs	claim
37	93	The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays	claim
38	92	The Partition into Hypercontexts Problem for Hyperreconfigurable Architectures	claim
39	90	Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis	claim
40	90	Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation	claim
41	89	HW/SW Co-design by Automatic Embedding of Complex IP Cores	claim
42	88	Automated Mapping of Coarse-Grain Pipelined Applications to FPGA Systems	claim
43	88	Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer	claim
44	87	Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs	claim
45	87	A Dynamic NoC Approach for Communication in Reconfigurable Devices	claim
46	84	Large Scale Protein Sequence Alignment Using FPGA Reprogrammable Logic Devices	claim
47	83	System-Level Modeling of Dynamically Reconfigurable Co-processors	claim
48	81	Design and Implementation of the Memory Scheduler for the PC-Based Router	claim
49	81	Power Analysis Attacks Against FPGA Implementations of the DES	claim
50	80	Secure Logic Synthesis	claim
51	75	Multiple Restricted Multiplication	claim
52	75	Wavelet-Based Image Compression on the Reconfigurable Computer ACE-V	claim
53	74	A Structured Methodology for System-on-an-FPGA Design	claim
54	74	Hardware/Software Implementation of FPGA-Targeted Matrix-Oriented SAT Solvers	claim
55	72	Simultaneous Timing Driven Clustering and Placement for FPGAs	claim
56	67	A Key Management Architecture for Securing Off-Chip Data Transfers	claim

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