FPL 2006 - PDF Preprint Papers

FPL 2006 International Conference on Field Programmable Logic and Applications

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FPL
2006
Springer

242views Hardware» more FPL 2006»

TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs

13 years 8 months ago

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With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...

Manuel Saldaña, Paul Chow

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Id	Views	Title	Status

1	242	TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs	claim
2	223	From Equation to VHDL: Using Rewriting Logic for Automated Function Generation	claim
3	219	FPGA Implementations of the DES and Triple-DES Masked Against Power Analysis Attacks	claim
4	211	Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description	claim
5	208	Implementation in Fpgas of Jacobi Method to Solve the Eigenvalue and Eigenvector Problem	claim
6	169	An FPGA-Based Electronic Cochlea with Dual Fixed-Point Arithmetic	claim
7	161	Predictive Load Balancing for Interconnected FPGAs	claim
8	158	Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed	claim
9	158	Placing Functionality in Fault-Tolerant Hardware/Software Reconfigurable Networks	claim
10	156	Improving Usability of FPGA-Based Reconfigurable Computers Through Operating System Support	claim
11	147	Efficient Automated Synthesis, Programing, and Implementation of Multi-Processor Platforms on FPGA Chips	claim
12	147	Non-Uniform Random Number Generation Through Piecewise Linear Approximations	claim
13	147	Secure Content Distribution System Based on Run-Time Partial Hardware Reconfiguration	claim
14	140	A Thermal Management and Profiling Method for Reconfigurable Hardware Applications	claim
15	140	Architectural Modifications to Improve Floating-Point Unit Efficiency in FPGAs	claim
16	137	FPGA Performance Optimization Via Chipwise Placement Considering Process Variations	claim
17	135	FPGA Design Considerations in the Implementation of a Fixed-Throughput Sphere Decoder for MIMO Systems	claim
18	132	Adaptive FPGAs: High-Level Architecture and a Synthesis Method	claim
19	129	Architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays	claim
20	129	A Reconfigurable Viterbi Decoder for a Communication Platform	claim
21	127	On-FPGA Communication Architectures and Design Factors	claim
22	127	FPGA Vendor Agnostic True Random Number Generator	claim
23	125	Application-Specific Memory Interleaving for FPGA-Based Grid Computations: A General Design Technique	claim
24	124	A Dynamically Reconfigurable Queue Scheduler	claim
25	123	Improved Interpolation and System Integration for FPGA-Based Molecular Dynamics Simulations	claim
26	121	Evaluation and Design of Processor-Like Reconfigurable Architectures	claim
27	120	Regular Expression Software Deceleration for Intrusion Detection Systems	claim
28	119	The Entropy of FPGA Reconfiguration	claim
29	118	Activity Estimation for Field-Programmable Gate Arrays	claim
30	115	Executing Hardware as Parallel Software for Picoblaze Networks	claim
31	115	A Congestion Driven Placement Algorithm for FPGA Synthesis	claim
32	113	A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design	claim
33	112	Real-Time Video Pixel Matching	claim
34	111	A Simulation Platform for Reconfigurable Computing Research	claim
35	111	A-B Nodes Classification for Power Estimation	claim
36	108	Implementation of Network Application Layer Parser for Multiple TCP/IP Flows in Reconfigurable Devices	claim
37	105	A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access	claim
38	103	A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification	claim
39	103	Modular Partitioning for Incremental Compilation	claim
40	103	An Efficient Fault Tolerance Scheme for Preventing Single Event Disruptions in Reconfigurable Architectures	claim
41	99	Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs	claim
42	99	Identifying FPGA IP-Cores Based on Lookup Table Content Analysis	claim
43	98	Self-Reconfigurable Pervasive Platform for Cryptographic Application	claim
44	96	Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding	claim
45	96	High Speed Document Clustering in Reconfigurable Hardware	claim
46	95	Automation of IP Core Interface Generation for Reconfigurable Computing	claim
47	95	A Reconfigurable Functional Unit for an Adaptive Dynamic Extensible Processor	claim
48	94	Sizing of Processing Arrays for FPGA-Based Computation	claim
49	91	Multi-Bit Carry Chains for High-Performance Reconfigurable Fabrics	claim
50	91	Reconfigurable Systems Enabled by a Network-on-Chip	claim
51	87	Using Reconfigurable HW for High Dimensional CAF Computation	claim
52	85	High-Performance and Parameterized Matrix Factorization on FPGAs	claim
53	81	A Dynamic Reconfigurable Fabric for Platform SoCs	claim
54	80	A Compiler Intermediate Representation for Reconfigurable Fabrics	claim
55	66	Minimizing Communication Cost for Reconfigurable Slot Modules	claim

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