FPL 2008 - PDF Preprint Papers

FPL 2008 International Conference on Field Programmable Logic and Applications

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FPL
2008
Springer

254views Hardware» more FPL 2008»

Digital hilbert transformers for FPGA-based phase-locked loops

13 years 6 months ago

Download www.esa.informatik.tu-darmstadt.de

The phase detector is a main building block in phaselocked loop (PLL) applications. FPGAs permit the realtime implementation of the CORDIC algorithm which offers an efficient solu...

Martin Kumm, M. Shahab Sanjari

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Id	Views	Title	Status

1	254	Digital hilbert transformers for FPGA-based phase-locked loops	claim
2	207	Bitstream compression techniques for Virtex 4 FPGAs	claim
3	193	Decimal multiplier on FPGA using embedded binary multipliers	claim
4	180	Compiled hardware acceleration of Molecular Dynamics code	claim
5	178	High-speed regular expression matching engine using multi-character NFA	claim
6	175	File system access from reconfigurable FPGA hardware processes in BORPH	claim
7	163	Towards an "early neural circuit simulator": A FPGA implementation of processing in the rat whisker system	claim
8	157	Chosen-message SPA attacks against FPGA-based RSA hardware implementations	claim
9	154	Numerical function generators using bilinear interpolation	claim
10	153	FPGA acceleration of quasi-Monte Carlo in finance	claim
11	153	Exploring FPGA network on chip implementations across various application and network loads	claim
12	150	Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs	claim
13	143	Fast toggle rate computation for FPGA circuits	claim
14	141	An analytical model describing the relationships between logic architecture and FPGA density	claim
15	138	An efficient run-time router for connecting modules in FPGAS	claim
16	137	FPGA acceleration of Monte-Carlo based credit derivative pricing	claim
17	131	Enhancing COPACOBANA for advanced applications in cryptography and cryptanalysis	claim
18	129	FPGA: The future platform for transforming, transporting and computing data	claim
19	129	Power reduction techniques for Dynamically Reconfigurable Processor Arrays	claim
20	126	Customized Reconfigurable Interconnection Networks for multiple application SOCS	claim
21	125	Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks	claim
22	124	Direct sigma-delta modulated signal processing in FPGA	claim
23	122	Mining Association Rules with systolic trees	claim
24	120	An FPGA-based implementation of the MINRES algorithm	claim
25	119	Polymorphic wavelet architectures using reconfigurable hardware	claim
26	119	An FPGA-based high-speed, low-latency trigger processor for high-energy physics	claim
27	117	On-the-fly attestation of reconfigurable hardware	claim
28	117	A versatile hardware architecture for a CFAR detector based on a linear insertion sorter	claim
29	116	Shared reconfigurable architectures for CMPS	claim
30	116	NOC architecture design for multi-cluster chips	claim
31	113	Mapping and scheduling with task clustering for heterogeneous computing systems	claim
32	112	Secure FPGA configuration architecture preventing system downgrade	claim
33	112	Fault tolerant methods for reliability in FPGAs	claim
34	111	Sampling from the exponential distribution using independent Bernoulli variates	claim
35	111	Hyperreconfigurable architectures	claim
36	110	Automatic generation of run-time parameterizable configurations	claim
37	110	Metawire: Using FPGA configuration circuitry to emulate a Network-on-Chip	claim
38	109	Loop unrolling and shifting for reconfigurable architectures	claim
39	107	Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA	claim
40	105	Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems	claim
41	104	FPGA family composition and effects of specialized blocks	claim
42	104	A technique for minimizing power during FPGA placement	claim
43	103	No-break dynamic defragmentation of reconfigurable devices	claim
44	100	A portable abstraction layer for hardware threads	claim
45	99	ATCA-based computation platform for data acquisition and triggering in particle physics experiments	claim
46	98	Comparing throughput and power consumption in both sequential and reconfigurable processors	claim
47	98	Rapid estimation of power consumption for hybrid FPGAs	claim
48	96	Low-latency high-bandwidth HW/SW communication in a virtual memory environment	claim
49	96	Towards benchmarking energy efficiency of reconfigurable architectures	claim
50	94	Acceleration of a production rigid molecule docking code	claim
51	92	Increasing the level of abstraction in FPGA-based designs	claim
52	92	Parallel hardware objects for dynamically partial reconfiguration	claim
53	91	Power efficient DSP datapath configuration methodology for FPGA	claim
54	86	Instruction buffer mode for multi-context Dynamically Reconfigurable Processors	claim

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