FPL 2009 - PDF Preprint Papers

FPL 2009 International Conference on Field Programmable Logic and Applications

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FPL
2009
Springer

179views Hardware» more FPL 2009»

Building heterogeneous reconfigurable systems using threads

13 years 8 months ago

Download hthreads.csce.uark.edu

Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a software-like...

Jason Agron, David L. Andrews

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Id	Views	Title	Status

1	179	Building heterogeneous reconfigurable systems using threads	claim
2	172	Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors	claim
3	166	Modeling post-techmapping and post-clustering FPGA circuit depth	claim
4	162	A comparison of FPGA and FPAA technologies for a signal processing application	claim
5	162	Efficient particle-pair filtering for acceleration of molecular dynamics simulation	claim
6	161	A multi-FPGA architecture for stochastic Restricted Boltzmann Machines	claim
7	156	A highly scalable Restricted Boltzmann Machine FPGA implementation	claim
8	154	Compiler assisted runtime task scheduling on a reconfigurable computer	claim
9	152	Clock gating architectures for FPGA power reduction	claim
10	149	Reconfigurable fault tolerance: A framework for environmentally adaptive fault mitigation in space	claim
11	148	Comparing fine-grained performance on the Ambric MPPA against an FPGA	claim
12	145	Area estimation and optimisation of FPGA routing fabrics	claim
13	145	Run-time Partial Reconfiguration speed investigation and architectural design space exploration	claim
14	142	Cooperative multithreading in dynamically reconfigurable systems	claim
15	135	Fast critical sections via thread scheduling for FPGA-based multithreaded processors	claim
16	132	Binary Synthesis with multiple memory banks targeting array references	claim
17	132	A biophysically accurate floating point somatic neuroprocessor	claim
18	130	Tracking elephant flows in internet backbone traffic with an FPGA-based cache	claim
19	129	Self-organizing multi-cue fusion for FPGA-based embedded imaging	claim
20	120	Using 3D integration technology to realize multi-context FPGAs	claim
21	117	Data parallel FPGA workloads: Software versus hardware	claim
22	117	CNP: An FPGA-based processor for Convolutional Networks	claim
23	115	Recursion in reconfigurable computing: A survey of implementation approaches	claim
24	113	Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays	claim
25	113	Clock duplicity for high-precision timestamping in Gigabit Ethernet	claim
26	112	The evolution of architecture exploration of programmable devices	claim
27	107	An FPGA based verification platform for HyperTransport 3.x	claim
28	106	Coarse-grained dynamically reconfigurable architecture with flexible reliability	claim
29	106	Low power techniques for Motion Estimation hardware	claim
30	106	An ASIC perspective on FPGA optimizations	claim
31	105	Improving the quality of a Physical Unclonable Function using configurable Ring Oscillators	claim
32	105	Towards a viable out-of-order soft core: Copy-Free, checkpointed register renaming	claim
33	105	Run-time resource management in fault-tolerant network on reconfigurable chips	claim
34	104	A multi-layered XML schema and design tool for reusing and integrating FPGA IP	claim
35	103	Customizable domain-specific computing	claim
36	102	Macs: A Minimal Adaptive routing circuit-switched architecture for scalable and parametric NoCs	claim
37	101	An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure	claim
38	100	A virus scanning engine using a parallel finite-input memory machine and MPUs	claim
39	99	Exploiting fast carry-chains of FPGAs for designing compressor trees	claim
40	98	Optimal runtime reconfiguration strategies for systolic arrays	claim
41	96	Noise impact of single-event upsets on an FPGA-based digital filter	claim
42	91	Large multipliers with fewer DSP blocks	claim
43	90	A toolset for the analysis and optimization of motion estimation algorithms and processors	claim
44	86	Improving logic density through synthesis-inspired architecture	claim
45	85	Generating high-performance custom floating-point pipelines	claim
46	82	Program-driven fine-grained power management for the reconfigurable mesh	claim
47	79	A reconfigurable architecture for the Phylogenetic Likelihood Function	claim
48	78	FPGA-accelerated Information Retrieval: High-efficiency document filtering	claim
49	63	Towards a unique FPGA-based identification circuit using process variations	claim

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