GLVLSI 2006 - PDF Preprint Papers

GLVLSI 2006 Great Lakes Symposium on VLSI

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GLVLSI
2006
IEEE

193views VLSI» more GLVLSI 2006»

Optimizing noise-immune nanoscale circuits using principles of Markov random fields

13 years 10 months ago

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As CMOS devices and operating voltages are scaled down, noise and defective devices will impact the reliability of digital circuits. Probabilistic computing compatible with CMOS o...

Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...

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Id	Views	Title	Status

1	193	Optimizing noise-immune nanoscale circuits using principles of Markov random fields	claim
2	185	Application of fast SOCP based statistical sizing in the microprocessor design flow	claim
3	165	Block alignment in 3D floorplan using layered TCG	claim
4	155	Dynamic voltage scaling for multitasking real-time systems with uncertain execution time	claim
5	152	2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology	claim
6	145	Leakage current starved domino logic	claim
7	144	Crosstalk analysis in nanometer technologies	claim
8	143	SACI: statistical static timing analysis of coupled interconnects	claim
9	142	Dynamic instruction schedulers in a 3-dimensional integration technology	claim
10	133	Design approaches for hybrid CMOS/molecular memory based on experimental device data	claim
11	129	Delay and peak power minimization for on-chip buses using temporal redundancy	claim
12	126	Hardware/software partitioning of operating systems: a behavioral synthesis approach	claim
13	124	Dominator-based partitioning for delay optimization	claim
14	120	Sensitivity evaluation of global resonant H-tree clock distribution networks	claim
15	119	Thermal analysis of a 3D die-stacked high-performance microprocessor	claim
16	119	PWAM signalling scheme for high speed serial link transceiver design	claim
17	115	Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology	claim
18	113	Statistical gate delay calculation with crosstalk alignment consideration	claim
19	112	A simulation methodology for reliability analysis in multi-core SoCs	claim
20	112	A design methodology for temperature variation insensitive low power circuits	claim
21	110	Synthesis of a wideband low noise amplifier	claim
22	105	A practical approach for monitoring analog circuits	claim
23	101	A digit serial algorithm for the integer power operation	claim
24	101	Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies	claim
25	98	Rapid intermodulation distortion estimation in fully balanced weakly nonlinear Gm-C filters using state-space modeling	claim
26	95	Test generation using SAT-based bounded model checking for validation of pipelined processors	claim
27	90	Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs	claim
28	87	Maximum effective distance of on-chip decoupling capacitors in power distribution grids	claim
29	83	Effects of process and environmental variations on timing characteristics of clocked registers	claim

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