GLVLSI 2011 - PDF Preprint Papers

GLVLSI 2011 Great Lakes Symposium on VLSI

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GLVLSI
2011
IEEE

91views VLSI» more GLVLSI 2011»

Circuit design of a dual-versioning L1 data cache for optimistic concurrency

9 months 5 days ago

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This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...

Azam Seyedi, Adrià Armejach, Adrián ...

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Id	Read	Views	Title	Status
1		91	Circuit design of a dual-versioning L1 data cache for optimistic concurrency	claim
2		78	Design of low-power multiple constant multiplications using low-complexity minimum depth operations	claim

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