HPCA 2009 - PDF Preprint Papers

HPCA 2009 International Symposium on High-Performance Computer Architecture

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HPCA
2009
IEEE

177views Distributed And Parallel Com...» more HPCA 2009»

Prediction router: Yet another low latency on-chip router architecture

2 years 2 months ago

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Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...

Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...

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Id	Views	Title	Status
1	177	Prediction router: Yet another low latency on-chip router architecture	claim
2	140	Adaptive Spill-Receive for robust high-performance caching in CMPs	claim
3	135	MRR: Enabling fully adaptive multicast routing for CMP interconnection networks	claim
4	122	Architectural Contesting	claim
5	116	A low-radix and low-diameter 3D interconnection network design	claim
6	91	A novel architecture of the 3D stacked MRAM L2 cache for CMPs	claim
7	88	PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches	claim
8	85	Feedback mechanisms for improving probabilistic memory prefetching	claim
9	82	In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects	claim
10	82	Criticality-based optimizations for efficient load processing	claim
11	75	Hardware-software integrated approaches to defend against software cache-based side channel attacks	claim
12	73	Variation-aware dynamic voltage/frequency scaling	claim
13	71	Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs	claim
14	66	Design and implementation of software-managed caches for multicores with local memory	claim
15	62	Soft error vulnerability aware process variation mitigation	claim
16	59	Accurate microarchitecture-level fault modeling for studying hardware faults	claim
17	59	A first-order fine-grained multithreaded throughput model	claim
18	59	Lightweight predication support for out of order processors	claim
19	59	Fast complete memory consistency verification	claim
20	59	Practical off-chip meta-data for temporal memory streaming	claim
21	58	Blueshift: Designing processors for timing speculation from the ground up	claim
22	58	Elastic-buffer flow control for on-chip networks	claim
23	56	Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems	claim
24	55	Dacota: Post-silicon validation of the memory subsystem in multi-core designs	claim
25	55	Express Cube Topologies for on-Chip Interconnects	claim
26	55	Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy	claim
27	54	Voltage emergency prediction: Using signatures to reduce operating margins	claim
28	54	Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches	claim
29	52	Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics	claim
30	52	iCFP: Tolerating all-level cache misses in in-order processors	claim
31	51	Reconciling specialization and flexibility through compound circuits	claim
32	46	Bridging the computation gap between programmable processors and hardwired accelerators	claim
33	45	Eliminating microarchitectural dependency from Architectural Vulnerability	claim

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