HPCA 2009 - PDF Preprint Papers

HPCA 2009 International Symposium on High-Performance Computer Architecture

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HPCA
2009
IEEE

328views Distributed And Parallel Com...» more HPCA 2009»

Prediction router: Yet another low latency on-chip router architecture

14 years 5 months ago

Download www.am.ics.keio.ac.jp

Network-on-Chips (NoCs) are quite latency sensitive, since their communication latency strongly affects the application performance on recent many-core architectures. To reduce th...

Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...

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Id	Views	Title	Status

1	328	Prediction router: Yet another low latency on-chip router architecture	claim
2	308	Adaptive Spill-Receive for robust high-performance caching in CMPs	claim
3	277	Architectural Contesting	claim
4	263	Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs	claim
5	249	MRR: Enabling fully adaptive multicast routing for CMP interconnection networks	claim
6	228	Accurate microarchitecture-level fault modeling for studying hardware faults	claim
7	212	A low-radix and low-diameter 3D interconnection network design	claim
8	200	A novel architecture of the 3D stacked MRAM L2 cache for CMPs	claim
9	200	Hardware-software integrated approaches to defend against software cache-based side channel attacks	claim
10	186	Criticality-based optimizations for efficient load processing	claim
11	180	Feedback mechanisms for improving probabilistic memory prefetching	claim
12	176	Design and implementation of software-managed caches for multicores with local memory	claim
13	176	Soft error vulnerability aware process variation mitigation	claim
14	175	Dacota: Post-silicon validation of the memory subsystem in multi-core designs	claim
15	174	Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics	claim
16	172	Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy	claim
17	171	Express Cube Topologies for on-Chip Interconnects	claim
18	166	PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches	claim
19	166	Bridging the computation gap between programmable processors and hardwired accelerators	claim
20	163	In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects	claim
21	160	Blueshift: Designing processors for timing speculation from the ground up	claim
22	159	Fast complete memory consistency verification	claim
23	156	Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems	claim
24	151	iCFP: Tolerating all-level cache misses in in-order processors	claim
25	150	Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches	claim
26	145	Lightweight predication support for out of order processors	claim
27	141	Variation-aware dynamic voltage/frequency scaling	claim
28	141	Elastic-buffer flow control for on-chip networks	claim
29	138	Voltage emergency prediction: Using signatures to reduce operating margins	claim
30	133	A first-order fine-grained multithreaded throughput model	claim
31	132	Practical off-chip meta-data for temporal memory streaming	claim
32	127	Eliminating microarchitectural dependency from Architectural Vulnerability	claim
33	123	Reconciling specialization and flexibility through compound circuits	claim

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