ICCAD 1993 - PDF Preprint Papers

ICCAD 1993 International Conference on Computer-Aided Design

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed ICCAD-1993 Paper

click to vote

ICCAD
1993
IEEE

141views Hardware» more ICCAD 1993»

Boolean matching for full-custom ECL gates

13 years 8 months ago

Download www.hpl.hp.com

Robert N. Mayo, Hervé J. Touati

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	141	Boolean matching for full-custom ECL gates	claim
2	139	Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processors	claim
3	134	Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs	claim
4	123	Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models	claim
5	121	Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures	claim
6	120	Latchup-aware placement and parasitic-bounded routing of custom analog cells	claim
7	120	Merging multiple FSM controllers for DFT/BIST hardware	claim
8	112	Piecewise linear models for Rsim	claim
9	112	Behavior tables: a basis for system representation and transformational system synthesis	claim
10	111	Unifying synchronous/asynchronous state machine synthesis	claim
11	108	Exact evaluation of memory size for multi-dimensional signal processing systems	claim
12	104	Parallel timing simulation on a distributed memory multiprocessor	claim
13	101	Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits	claim
14	101	Convexity-based algorithms for design centering	claim
15	100	Macromodeling of the A.C. characteristics of CMOS Op-amps	claim
16	97	High level synthesis for reconfigurable datapath structures	claim
17	85	Input don't care sequences in FSM networks	claim
18	81	Instruction set mapping for performance optimization	claim
19	81	Inverter minimization in multi-level logic networks	claim
20	77	Reconfigurable scan chains: a novel approach to reduce test application time	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers