ICCAD 1995 - PDF Preprint Papers

ICCAD 1995 International Conference on Computer-Aided Design

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ICCAD
1995
IEEE

180views Hardware» more ICCAD 1995»

Design based analog testing by Characteristic Observation Inference

13 years 8 months ago

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In this paper, a new approach to analog test design based on the circuit design process, called Characteristic Observation Inference (COI), is presented. In many situations, it is...

Walter M. Lindermeir, Helmut E. Graeb, Kurt Antrei...

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Id	Views	Title	Status

1	180	Design based analog testing by Characteristic Observation Inference	claim
2	170	Acceleration techniques for dynamic vector compaction	claim
3	167	A novel methodology for statistical parameter extraction	claim
4	163	Signal integrity optimization on the pad assignment for high-speed VLSI design	claim
5	144	Background memory management for dynamic data structure intensive processing systems	claim
6	140	Bounded-skew clock and Steiner routing under Elmore delay	claim
7	136	A controller-based design-for-testability technique for controller-data path circuits	claim
8	135	An iterative improvement algorithm for low power data path synthesis	claim
9	134	A delay model for logic synthesis of continuously-sized networks	claim
10	129	Activity-driven clock design for low power circuits	claim
11	127	Hybrid decision diagrams	claim
12	120	Pattern generation for a deterministic BIST scheme	claim
13	118	Impulse response fault model and fault extraction for functional level analog circuit diagnosis	claim
14	114	Sequential synthesis using S1S	claim
15	113	Logic decomposition during technology mapping	claim
16	110	Fast functional simulation using branching programs	claim
17	108	Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels	claim
18	106	Re-engineering of timing constrained placements for regular architectures	claim
19	97	Interface co-synthesis techniques for embedded systems	claim
20	97	APPlaUSE: Area and performance optimization in a unified placement and synthesis environment	claim
21	96	Delay optimal partitioning targeting low power VLSI circuits	claim
22	95	A sequential quadratic programming approach to concurrent gate and wire sizing	claim
23	94	Test register insertion with minimum hardware cost	claim
24	92	Linear decomposition algorithm for VLSI design applications	claim
25	90	An optimal algorithm for area minimization of slicing floorplans	claim
26	90	Design-for-debugging of application specific designs	claim
27	88	Estimation and bounding of energy consumption in burst-mode control circuits	claim
28	88	LOT: logic optimization with testability-new transformations using recursive learning	claim
29	84	Statistical behavioral modeling and characterization of A/D converters	claim
30	84	Single-layer fanout routing and routability analysis for Ball Grid Arrays	claim
31	79	Optimal wire sizing and buffer insertion for low power and a generalized delay model	claim
32	78	A unified approach to topology generation and area optimization of general floorplans	claim
33	77	Optimal wiresizing for interconnects with multiple sources	claim
34	77	PARAS: system-level concurrent partitioning and scheduling	claim
35	76	Design verification via simulation and automatic test pattern generation	claim
36	69	Binary decision diagrams and beyond: enabling technologies for formal verification	claim
37	68	Generating sparse partial inductance matrices with guaranteed stability	claim
38	68	Pseudo-random testing and signature analysis for mixed-signal circuits	claim
39	67	Fault emulation: a new approach to fault grading	claim
40	65	Symbolic hazard-free minimization and encoding of asynchronous finite state machines	claim
41	61	Stable and efficient reduction of substrate model networks using congruence transforms	claim

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