ICCD 2004 - PDF Preprint Papers

ICCD 2004 International Conference on Computer Design

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed ICCD-2004 Paper

click to vote

ICCD
2004
IEEE

172views Hardware» more ICCD 2004»

A Signal Integrity Test Bed for PCB Buses

14 years 1 months ago

Download iccd.et.tudelft.nl

Research in high-speed interconnect requires physical test to validate circuit models and design assumptions. At multi-Gbit/sec rates, physical implementations require custom circ...

Jihong Ren, Mark R. Greenstreet

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	172	A Signal Integrity Test Bed for PCB Buses	claim
2	158	An Embedded Reconfigurable SIMD DSP with Capability of Dimension-Controllable Vector Processing	claim
3	154	A High-Frequency Decimal Multiplier	claim
4	154	Transistor and Pin Reordering for Gate Oxide Leakage Reduction in Dual T{ox} Circuits	claim
5	149	Adaptive Selection of an Index in a Texture Cache	claim
6	148	Many-to-Many Core-Switch Mapping in 2-D Mesh NoC Architectures	claim
7	141	An Architectural Power Estimator for Analog-to-Digital Converters	claim
8	138	A Novel Low-Power Scan Design Technique Using Supply Gating	claim
9	138	Design and Implementation of Scalable Low-Power Montgomery Multiplier	claim
10	137	Comparative Study of Strategies for Formal Verification of High-Level Processors	claim
11	135	Design Methodologies and Architecture Solutions for High-Performance Interconnects	claim
12	134	An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks	claim
13	132	Compressed Embedded Diagnosis of Logic Cores	claim
14	131	3D Processing Technology and Its Impact on iA32 Microprocessors	claim
15	129	Cache Array Architecture Optimization at Deep Submicron Technologies	claim
16	128	Static Transition Probability Analysis Under Uncertainty	claim
17	126	Implementation of Fine-Grained Cache Monitoring for Improved SMT Scheduling	claim
18	125	IPC Driven Dynamic Associative Cache Architecture for Low Energy	claim
19	123	Software/Network Co-Simulation of Heterogeneous Industrial Networks Architectures	claim
20	123	Compiler-Based Frame Formation for Static Optimization	claim
21	122	Quality Improvement Methods for System-Level Stimuli Generation	claim
22	122	Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures	claim
23	120	XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs	claim
24	119	I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design	claim
25	119	Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems	claim
26	119	An Accurate Combinatorial Model for Performance Prediction of Deterministic Wormhole Routing in Torus Multicomputer Systems	claim
27	119	Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing	claim
28	115	Generating Monitor Circuits for Simulation-Friendly GSTE Assertion Graphs	claim
29	115	ACG-Adjacent Constraint Graph for General Floorplans	claim
30	114	Low Energy, Highly-Associative Cache Design for Embedded Processors	claim
31	113	Functional Illinois Scan Design at RTL	claim
32	113	Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems	claim
33	113	End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths	claim
34	112	Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm	claim
35	112	Combined Channel Segmentation and Buffer Insertion for Routability and Performance Improvement of Field	claim
36	112	An Infrastructure IP for On-Chip Clock Jitter Measurement	claim
37	111	Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure	claim
38	111	Potential Slack Budgeting with Clock Skew Optimization	claim
39	109	Low Power Test Data Compression Based on LFSR Reseeding	claim
40	107	Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor	claim
41	107	Network-on-Chip: The Intelligence is in The Wire	claim
42	106	Extending the Applicability of Parallel-Serial Scan Designs	claim
43	106	Gate Sizing and V{t} Assignment for Active-Mode Leakage Power Reduction	claim
44	106	Energy Characterization of Hardware-Based Data Prefetching	claim
45	106	A New Statistical Optimization Algorithm for Gate Sizing	claim
46	105	Circuit-Based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation	claim
47	104	Exploiting Quiescent States in Register Lifetime	claim
48	103	A Two-Layer Bus Routing Algorithm for High-Speed Boards	claim
49	103	Design-Space Exploration of Power-Aware On/Off Interconnection Networks	claim
50	103	A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network	claim
51	101	Increasing Processor Performance Through Early Register Release	claim
52	100	Thermal-Aware Clustered Microarchitectures	claim
53	100	Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning	claim
54	100	A Minimal Dual-Core Speculative Multi-Threading Architecture	claim
55	99	An Efficient Algorithm for Reconfiguring Shared Spare RRAM	claim
56	98	Coping with The Variability of Combinational Logic Delays	claim
57	98	An Architecture for Fast Processing of Large Unstructured Data Sets	claim
58	98	Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture	claim
59	97	Runtime Execution Monitoring (REM) to Detect and Prevent Malicious Code Execution	claim
60	97	A General Post-Processing Approach to Leakage Current Reduction in SRAM-Based FPGAs	claim
61	96	Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study	claim
62	93	Reticle Floorplanning with Guaranteed Yield for Multi-Project Wafers	claim
63	91	FPGA Emulation of Quantum Circuits	claim
64	91	Diagnosis of Hold Time Defects	claim
65	89	Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed	claim
66	87	Evaluating Techniques for Exploiting Instruction Slack	claim
67	87	Fetch Halting on Critical Load Misses	claim
68	79	Using Circuits and Systems-Level Research to Drive Nanotechnology	claim
69	76	Technique to Eliminate Sorting in IP Packet Forwarding Devices	claim
70	74	Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2	claim
71	71	On-Chip Transparent Wire Pipelining	claim
72	64	Graph Automorphism-Based Algorithm for Determining Symmetric Inputs	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers