IEEEPACT 2005 - PDF Preprint Papers

IEEEPACT 2005 International Conference on Parallel Architectures and Compilation Techniques

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed IEEEPACT-2005 Paper

click to vote

IEEEPACT
2005
IEEE

177views Distributed And Parallel Com...» more IEEEPACT 2005»

Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window

13 years 10 months ago

Download www.cs.ucf.edu

Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...

Huiyang Zhou

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	177	Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window	claim
2	146	A Distributed Control Path Architecture for VLIW Processors	claim
3	137	Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors	claim
4	135	Characterization of TCC on Chip-Multiprocessors	claim
5	133	Memory Coloring: A Compiler Approach for Scratchpad Memory Management	claim
6	131	Communication Optimizations for Fine-Grained UPC Applications	claim
7	123	Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network Processor	claim
8	107	An Event-Driven Multithreaded Dynamic Optimization Framework	claim
9	104	Parallel Programming and Parallel Abstractions in Fortress	claim
10	103	Extended Whole Program Paths	claim
11	101	Instruction Based Memory Distance Analysis and its Application	claim
12	100	HUNTing the Overlap	claim
13	99	Compiler Directed Early Register Release	claim
14	97	Performance Analysis of System Overheads in TCP/IP Workloads	claim
15	95	Memory State Compressors for Giga-Scale Checkpoint/Restore	claim
16	94	Trace Cache Sampling Filter	claim
17	94	Data Centric Transformations on Non-Integer Iteration Spaces	claim
18	92	A Simple Divide-and-Conquer Approach for Neural-Class Branch Prediction	claim
19	91	Store-Ordered Streaming of Shared Memory	claim
20	84	Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors	claim
21	75	Automatic Tuning Matrix Multiplication Performance on Graphics Hardware	claim
22	63	Maximizing CMP Throughput with Mediocre Cores	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers