ISCA 2009 - PDF Preprint Papers

ISCA 2009 International Symposium on Computer Architecture

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ISCA
2009
IEEE

318views Hardware» more ISCA 2009»

Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors

13 years 11 months ago

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With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...

Abhishek Bhattacharjee, Margaret Martonosi

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Id	Views	Title	Status

1	318	Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors	claim
2	276	PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches	claim
3	239	Scalable high performance main memory system using phase-change memory technology	claim
4	230	Architecting phase change memory as a scalable dram alternative	claim
5	214	Phastlane: a rapid transit optical routing network	claim
6	201	A memory system design framework: creating smart memories	claim
7	199	Ten ways to waste a parallel computer	claim
8	199	SigRace: signature-based data race detection	claim
9	192	A case for bufferless routing in on-chip networks	claim
10	189	Hybrid cache architecture with disparate memory technologies	claim
11	186	Application-aware deadlock-free oblivious routing	claim
12	180	Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices	claim
13	178	Thread motion: fine-grained power management for multi-core systems	claim
14	173	A fault tolerant, area efficient architecture for Shor's factoring algorithm	claim
15	161	AnySP: anytime anywhere anyway signal processing	claim
16	159	End-to-end register data-flow continuous self-test	claim
17	158	Boosting single-thread performance in multi-core systems through fine-grain multi-threading	claim
18	153	Indirect adaptive routing on large scale interconnection networks	claim
19	152	Scaling the bandwidth wall: challenges in and avenues for CMP scaling	claim
20	150	Stream chaining: exploiting multiple levels of correlation in data prefetching	claim
21	148	Disaggregated memory for expansion and sharing in blade servers	claim
22	148	Memory mapped ECC: low-cost error protection for last level caches	claim
23	146	Multi-execution: multicore caching for data-similar executions	claim
24	146	Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor	claim
25	144	Dynamic MIPS rate stabilization in out-of-order processors	claim
26	144	Dynamic performance tuning for speculative threads	claim
27	143	Spatio-temporal memory streaming	claim
28	140	Flexible reference-counting-based hardware acceleration for garbage collection	claim
29	139	Reactive NUCA: near-optimal block placement and replication in distributed caches	claim
30	138	Achieving predictable performance through better memory controller placement in many-core CMPs	claim
31	138	Hardware support for WCET analysis of hard real-time multicore systems	claim
32	137	A case for an interleaving constrained shared-memory multi-processor	claim
33	136	ECMon: exposing cache events for monitoring	claim
34	136	Architectural core salvaging in a multi-core processor for hard-error tolerance	claim
35	123	InvisiFence: performance-transparent memory ordering in conventional multiprocessors	claim
36	118	Temperature-constrained power control for chip multiprocessors with online model estimation	claim

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