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ISCAS 2005 International Symposium on Circuits and Systems

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ISCAS
2005
IEEE

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A low dropout, CMOS regulator with high PSR over wideband frequencies

13 years 10 months ago

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Modern System-on-Chip (SoC) environments are swamped in high frequency noise that is generated by RF and digital circuits and propagated onto supply rails through capacitive coupli...

Vishal Gupta, Gabriel A. Rincón-Mora

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Id	Views	Title	Status

1	275	A low dropout, CMOS regulator with high PSR over wideband frequencies	claim
2	273	A distributed slack bus model and its impact on distribution system application techniques	claim
3	247	Digital signal processing engine design for polar transmitter in wireless communication systems	claim
4	231	Resonant DC/DC converter with class E oscillator	claim
5	229	Comparison of two class E amplifiers for EER transmitter	claim
6	224	A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter	claim
7	218	Scalable multiview video coding using wavelet	claim
8	214	Blind separation of statistically independent signals with mixed sub-Gaussian and super-Gaussian probability distributions	claim
9	209	Low complexity H.263 to H.264 video transcoding using motion vector decomposition	claim
10	207	A novel low-power input-independent MOS AC/DC charge pump	claim
11	205	Viewpoint switching in multiview video streaming	claim
12	199	Congestion-optimized scheduling of video over wireless ad hoc networks	claim
13	197	Averaging attack resilient video fingerprinting	claim
14	196	An interference rejection filter for an ultra-wideband quadrature downconversion autocorrelation receiver	claim
15	196	Arbitrary scale image enlargement with the prediction of high frequency components	claim
16	192	A sub-1V bandgap reference circuit using subthreshold current	claim
17	191	Behavioural modeling and simulation of a switched-current phase locked loop	claim
18	190	Digital VLSI OFDM transceiver architecture for wireless SoC design	claim
19	190	Using CLNS for FFTs in OFDM demodulation of UWB receivers	claim
20	190	A complete receiver solution for a chaotic direct-sequence spread spectrum communication system	claim
21	187	New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination	claim
22	187	Built-in self-test for automatic analog frequency response measurement	claim
23	187	Hybrid cascode compensation for two-stage CMOS operational amplifiers	claim
24	185	2 GHz 8-bit CMOS ROM-less direct digital frequency synthesizer	claim
25	184	An adaptive, truly background calibration method for high speed pipeline ADC design	claim
26	183	Battery-aware dynamic voltage scaling in multiprocessor embedded system	claim
27	182	A new reconfigurable modem architecture for 3G multi-standard wireless communication systems	claim
28	182	Efficient search and mode prediction algorithms for motion estimation in H.264/AVC	claim
29	181	Adjustable gamma correction circuit for TFT LCD	claim
30	181	Wide frequency range voltage controlled ring oscillators based on transmission gates	claim
31	179	Robust stabilization of control systems using piecewise linear Lyapunov functions and evolutionary algorithm	claim
32	178	Lifting-based multi-view image coding	claim
33	177	A combined two's complement and floating-point comparator	claim
34	177	Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS)	claim
35	175	New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation	claim
36	173	Slack-time aware routing in NoC systems	claim
37	173	Decentralized energy-conserving and coverage-preserving protocols for wireless sensor networks	claim
38	173	CMOS contact imager for monitoring cultured cells	claim
39	172	A digital CMOS DNA chip	claim
40	171	Compressed-domain fall incident detection for intelligent home surveillance	claim
41	171	Image transmission over IEEE 802.15.4 and ZigBee networks	claim
42	170	Quantized LDPC decoder design for binary symmetric channels	claim
43	168	Is home network application acceptable or not?	claim
44	168	A 0.8V Delta-Sigma modulator using DTMOS technique	claim
45	167	A novel 2D filter design methodology	claim
46	167	A 33.2M vertices/sec programmable geometry engine for multimedia embedded systems	claim
47	167	Low-power log-MAP turbo decoding based on reduced metric memory access	claim
48	166	Extending SystemC to support mixed discrete-continuous system modeling and simulation	claim
49	165	An area-efficient and protected network interface for processing-in-memory systems	claim
50	164	A 3-way SIMD engine for programmable triangle setup in embedded 3D graphics hardware	claim
51	164	An improved rate control algorithm for H.264	claim
52	163	An energy-efficient charge recycling approach for a SAR converter with capacitive DAC	claim
53	163	A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip	claim
54	163	Shot change detection on H.264/AVC compressed video	claim
55	162	Capacitive coupling of data and power for 3D silicon-on-insulator VLSI	claim
56	162	Pulse modulation CMOS image sensor for bio-fluorescence imaging applications	claim
57	161	A traffic aware, energy efficient MAC protocol for wireless sensor networks	claim
58	161	LMI-based neurocontroller for guaranteed cost control of uncertain time-delay systems	claim
59	161	Fast pixel-based video scene change detection	claim
60	159	A low power FPGA routing architecture	claim
61	159	A low-power, 20-Gb/s continuous-time adaptive passive equalizer	claim
62	159	A Fourier series-based RLC interconnect model for periodic signals	claim
63	158	Designing optimized pipelined global interconnects: algorithms and methodology impact	claim
64	157	High-efficiency power amplifier for wireless sensor networks	claim
65	157	Analog complex wavelet filters	claim
66	156	Jitter equalization for binary baseband communication	claim
67	156	Optimal 2 sub-bank memory architecture for bit plane coder of JPEG2000	claim
68	155	A new CMOS wideband RF front-end for multistandard low-IF wireless receivers	claim
69	155	A low complexity motion compensated frame interpolation method	claim
70	155	Hyperblock formation: a power/energy perspective for high performance VLIW architectures	claim
71	154	Boost-buck inverter variable structure control for grid-connected photovoltaic systems	claim
72	154	Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters	claim
73	154	HIBI-based multiprocessor SoC on FPGA	claim
74	154	Back propagation learning of neural networks with chaotically-selected affordable neurons	claim
75	154	Fast 802.11 link adaptation for real-time video streaming by cross-layer signaling	claim
76	154	An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays	claim
77	153	A RAM-based FPGA implementation of the 64-bit MISTY1 block cipher	claim
78	153	A two-step DDEM ADC for accurate and cost-effective DAC testing	claim
79	152	Robust watermarking of music signals by cepstrum modification	claim
80	152	Dictionary-based program compression on transport triggered architectures	claim
81	152	Error resilient content-based image authentication over wireless channel	claim
82	150	Joint compensation of IQ-imbalance and carrier phase synchronization errors in communication receivers	claim
83	150	High speed pilot-less sampling frequency acquisition for DMT systems	claim
84	149	A 110 dB CMRR/PSRR/gain CMOS operational amplifier	claim
85	149	Audio source separation by source localization with Hilbert spectrum	claim
86	149	Advances in QoS path(s) selection problem	claim
87	148	. Analog slice turbo decoding	claim
88	148	Clock and data recovery with adaptive loop gain for spread spectrum SerDes applications	claim
89	148	A novel 1.5V DC offset cancellation CMOS down conversion mixer	claim
90	147	A heuristic approach for multiple restricted multiplication	claim
91	147	A two-chip, 4-MHz, microelectromechanical reference oscillator	claim
92	146	A novel approach for network on chip emulation	claim
93	145	SoC platform based design of MPEG-2/4 AAC audio decoder	claim
94	145	A switched delay line based optical switch architecture with a bypass line	claim
95	144	A method for online secondary path modeling in active noise control systems	claim
96	144	Adaptive beamforming using uniform concentric circular arrays with frequency invariant characteristics	claim
97	144	Event-based imaging with active illumination in sensor networks	claim
98	144	Cascode buffer for monolithic voltage conversion operating at high input supply voltages	claim
99	144	Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis	claim
100	143	Design and FPGA implementation of a structure of evolutionary digital filters for hardware implementation	claim
101	143	Biasing techniques for subthreshold MOS resistive grids	claim
102	142	Hardware-based support vector machine classification in logarithmic number systems	claim
103	142	Fast region-of-interest transcoding for JPEG 2000 images	claim
104	142	Multichannel SVD-based image de-noising	claim
105	142	A class of novel blind source extraction algorithms based on a linear predictor	claim
106	142	Automatic video region-of-interest determination based on user attention model	claim
107	141	A low voltage CMOS multiplier for high frequency equalization	claim
108	141	Image compression using texture modeling	claim
109	141	Fast-scale instability of single-stage power-factor-correction power supplies	claim
110	141	Convergence analysis of a background interstage gain calibration technique for pipelined ADCs	claim
111	141	A CMOS capacitance sensor for cell adhesion characterization	claim
112	140	Macroblock-based algorithm for dual-bitstream MPEG video streaming with VCR functionalities	claim
113	140	Low energy asynchronous architectures	claim
114	140	A 16-bit low-power microcontroller with monolithic MEMS-LC clocking	claim
115	140	Drift-free multiple description video coding with redundancy rate-distortion optimization	claim
116	139	Design of multiplier-free state-space digital filters	claim
117	139	A musical-driven video summarization system using content-aware mechanisms	claim
118	139	The missing observations theorem and a new proof of Levinson's recursion	claim
119	139	A frequency-domain SIR maximizing time-domain equalizer for VDSL systems	claim
120	138	An 11M-triangles/sec 3D graphics clipping engine for triangle primitives	claim
121	138	An high speed integrated equalizer for dispersion compensation in 10Gb/s fiber networks	claim
122	138	A low spur fractional-N frequency synthesizer architecture	claim
123	138	Transition time bounded low-power clock tree construction	claim
124	138	Modeling of MOS transistors based on genetic algorithm and simulated annealing	claim
125	137	ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure	claim
126	137	Direct-digital synthesis using delta-sigma modulated signals	claim
127	136	Probabilistic computing with future deep sub-micrometer devices: a modelling approach	claim
128	136	A low-power visual horizon estimation chip	claim
129	136	Economical passive filter synthesis using genetic programming based on tree representation	claim
130	136	Architectures for ASIC implementations of low-density parity-check convolutional encoders and decoders	claim
131	136	Low complexity RDO mode decision based on a fast coding-bits estimation model for H.264/AVC	claim
132	135	S-code: new distance-3 MDS array codes	claim
133	135	Calculation of intermodulation distortion in CMOS transconductance stage	claim
134	135	Dual use of power lines for data communications in a system-on-chip environment	claim
135	134	Heap charge pump optimisation by a tapered architecture	claim
136	134	Video shot segmentation using fusion of SVD and mutual information features	claim
137	133	Minimal activity mixed-signal VLSI architecture for real-time linear transforms in video	claim
138	133	Approach for physical design in sub-100 nm era	claim
139	133	Multiobjective VLSI cell placement using distributed simulated evolution algorithm	claim
140	133	Sub-sequence video coding for improved temporal scalability	claim
141	132	High efficiency wide bandwidth power supplies for GSM and EDGE RF power amplifiers	claim
142	132	A high performance distributed-parallel-processor architecture for 3D IIR digital filters	claim
143	132	AER EAR: a matched silicon cochlea pair with address event representation interface	claim
144	132	N-scroll chaotic attractors from a general jerk circuit	claim
145	132	Parallelism/regularity-driven MIMO detection algorithm design	claim
146	131	Wavelet-based estimation of long-range dependence in MPEG video traces	claim
147	131	A low-complexity scanned-array 3D IIR frequency-planar filter	claim
148	131	Digitizing of UWB signals based on frequency channelization	claim
149	131	Timing yield estimation using statistical static timing analysis	claim
150	131	Blind signal separation into groups of dependent signals using joint block diagonalization	claim
151	131	A novel automatic white balance method for digital still cameras	claim
152	130	Smart bio-laboratories of the future	claim
153	130	Spatial error concealment based on directional decision and intra prediction	claim
154	130	RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction	claim
155	129	An analytical approach for soft error rate estimation in digital circuits	claim
156	129	Partitioning graphs of supply and demand	claim
157	129	Cryptanalysis of a multistage encryption system	claim
158	129	A reconfigurable architecture for scanning biosequence databases	claim
159	129	Boundary control of a bipolar square-wave generator using second-order switching surface	claim
160	129	Optimized decoding scheme for erroneous MPEG-4 FGS bitstream	claim
161	128	A low-power CMOS power amplifier for ultra wideband (UWB) applications	claim
162	128	Development of an audio player as system-on-a-chip using an open source platform	claim
163	128	A study of encoding and decoding techniques for syndrome-based video coding	claim
164	127	Directionally weighted color interpolation for digital cameras	claim
165	127	High performance error concealment algorithm by motion vector refinement for MPEG-4 video	claim
166	127	Wire-driven microarchitectural design space exploration	claim
167	127	Convergent micro-pipelines: a versatile operator for mixed asynchronous-synchronous computations	claim
168	127	A novel property of the second-order modes of discrete-time systems under variable transformation	claim
169	127	Energy and latency evaluation of NoC topologies	claim
170	127	A compact nA/V CMOS triode-transconductor and its application to very-low frequency filters	claim
171	127	Minimizing power with flexible voltage islands	claim
172	126	Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT	claim
173	126	Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits	claim
174	126	Image processing and interface for retinal visual prostheses	claim
175	126	Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation	claim
176	126	A distributed FIFO scheme for on chip communication	claim
177	126	CMOS sensor array for electrical imaging of neuronal activity	claim
178	125	Phase noise and amplitude issues of a wide-band VCO utilizing a switched tuning resonator	claim
179	125	A methodology for partitioning DSP applications in hybrid reconfigurable systems	claim
180	125	Integration of image stabilizer with video codec for digital video cameras	claim
181	125	Fixed-current method for programming large floating-gate arrays	claim
182	125	A novel algorithm of spatial scalability for scrambled video	claim
183	124	One-pass computation-aware motion estimation with adaptive search strategy	claim
184	124	Parallel FFT computation with a CDMA-based network-on-chip	claim
185	124	Timing-driven global routing with efficient buffer insertion	claim
186	124	High-order single-loop double-sampling sigma-delta modulator topologies for broadband applications	claim
187	123	Multiple project wafers for medium-volume IC production	claim
188	123	Jitter limitations on multi-carrier modulation	claim
189	123	Lower-bound estimation for multi-bitwidth scheduling	claim
190	123	Sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations	claim
191	122	Linear and nonlinear macromodels for power/signal integrity	claim
192	122	Towards a rigorous formulation of the space mapping technique for engineering design	claim
193	122	A memory-efficient deblocking filter for H.264/AVC video coding	claim
194	122	Stability of a shift-variant 2-D state-space digital filter	claim
195	122	A mixed analog-digital hybrid for speech enhancement purposes	claim
196	122	F-SEONS: a second-order frequency-domain algorithm for noisy convolutive source separation	claim
197	121	SET and RESET pulse characterization in BJT-selected phase-change memories	claim
198	121	On-board fault-tolerant SAR processor for spaceborne imaging radar systems	claim
199	121	On phase noise in quadrature cross-coupled oscillators	claim
200	121	A low-power high-SFDR CMOS direct digital frequency synthesizer	claim
201	121	Self-calibrating networks-on-chip	claim
202	121	Experimental verification of 3-D hysteresis multi-scroll chaotic attractors	claim
203	120	Nonlinear output feedback control of TCP/AQM networks	claim
204	120	Low voltage analog synthesizer of orthogonal signals: a current-mode approach	claim
205	119	Multi-plet two-channel perfect reconstruction filter banks	claim
206	119	Stroboscopic model and bifurcations in TCP/RED	claim
207	119	Analysis of power consumption in VLSI global interconnects	claim
208	118	A robust background calibration technique for switched-capacitor pipelined ADCs	claim
209	117	Architecture of global motion compensation for MPEG-4 advanced simple profile	claim
210	117	Electrical and optical on-chip interconnects in scaled microprocessors	claim
211	117	Peak-to-average power-ratio reduction algorithms for OFDM systems via constellation extension	claim
212	117	Linear transform based motion compensated prediction for luminance intensity changes	claim
213	117	A VLSI model of the bat dorsal nucleus of the lateral lemniscus for azimuthal echolocation	claim
214	117	A random-valued impulse noise detector using level detection	claim
215	117	Feedforward reversed nested Miller compensation techniques for three-stage amplifiers	claim
216	116	Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter	claim
217	115	Low power repeaters driving RLC interconnects with delay and bandwidth constraints	claim
218	115	Observed hybrid oscillations in an electrical distribution system	claim
219	115	Progressive scrambling for MP3 audio	claim
220	115	VLSI architecture based on packet data transfer scheme and its application	claim
221	115	An optimal tone reproduction curve operator for the display of high dynamic range images	claim
222	115	A framework for the design of error-aware power-efficient fixed-width Booth multipliers	claim
223	115	Power-aware slack distribution for hierarchical VLSI design	claim
224	114	RF-link for cortical neuroprosthesis	claim
225	114	A novel methodology for the design of LC tank VCO with low phase noise	claim
226	114	Self-organized cortical map formation by guiding connections	claim
227	114	Behavioural modelling, simulation, test and diagnosis of MEMS using ANNs	claim
228	114	Structured stochastic optimization strategies for problems with ill-conditioned error surfaces	claim
229	114	Accurate high frequency noise modeling in SiGe HBTs	claim
230	114	Performance analysis by topology indexed lookup tables	claim
231	113	On the robustness of an analog VLSI implementation of a time encoding machine	claim
232	113	Effect of traffic localization on energy dissipation in NoC-based interconnect	claim
233	113	A study of high-frequency regenerative frequency dividers	claim
234	113	The realization of a mismatch-free and 1.5-bit over-sampling pipelined ADC	claim
235	113	High tuning accuracy design of variable IIR filters as a cascade of identical sub-filters	claim
236	112	Field test results for low power bearing estimator sensor nodes	claim
237	112	Multiple resonance networks with incomplete energy transfer and operating with zero-state response	claim
238	112	A memory-reduced log-MAP kernel for turbo decoder	claim
239	112	Baseball event detection using game-specific feature sets and rules	claim
240	111	Necessary and sufficient conditions for LTI systems to preserve signal richness	claim
241	111	Spectral shaping of timing mismatches in time-interleaved analog-to-digital converters	claim
242	110	Controlling chaos in DC/DC converters using optimal resonant parametric perturbation	claim
243	109	A monolithic isolation amplifier in silicon-on-insulator CMOS	claim
244	108	Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity	claim
245	108	A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch	claim
246	108	A frequency synthesizer using two different delay feedbacks	claim
247	108	Noise coupling in multi-voltage power distribution systems with decoupling capacitors	claim
248	108	MIRROR: an interactive content based image retrieval system	claim
249	108	On VLSI decompositions for d-ary de Bruijn graphs (extended abstract)	claim
250	107	Discrete and continuous substrate noise spectrum dependence on digital circuit characteristics	claim
251	107	A sparsified vector potential equivalent circuit model for massively coupled interconnects	claim
252	107	Parameter domain pruning for improving convergence of synthesis algorithms	claim
253	107	A novel VLSI architecture for VBSME in MPEG-4 AVC/H.264	claim
254	106	kT/C constrained optimization of power in pipeline ADCs	claim
255	106	A generic multilevel multiplying D/A converter for pipelined ADCs	claim
256	106	A systematic approach to CMOS low noise amplifier design for ultrawideband applications	claim
257	105	Low-sensitivity current-mode active-RC filters using impedance tapering	claim
258	104	Behavioral modeling simulation and high-level synthesis of pipeline A/D converters	claim
259	104	On the three-dimensional channel routing	claim
260	104	Bifurcation in parallel-connected buck converters under current-mode control	claim
261	104	Optimum design of very low distortion class E power amplifiers	claim
262	103	Why area might reduce power in nanoscale CMOS	claim
263	103	Low-complexity adaptive algorithms for pre-distortion of power amplifiers	claim
264	103	Segmented channel routing with pin rearrangements via satisfiability	claim
265	103	A subtle link in switched dynamical systems: saddle-node bifurcation meets border collision	claim
266	103	Hardware realization of panoramic camera with speaker-oriented face extraction for teleconferencing	claim
267	101	Parallel algorithm for hardware implementation of inverse halftoning	claim
268	100	Some properties of generalized 2-D mirror image and anti mirror image polynomials	claim
269	100	Instrumentation of YSZ oxygen sensor calibration in liquid lead-bismuth eutectic	claim
270	100	A test strategy for time-to-digital converters using dynamic element matching and dithering	claim
271	99	On the implementation of 128-pt FFT/IFFT for high-performance WPAN	claim
272	99	Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture	claim
273	99	Concentrator access networks for programmable logic cores on SoCs	claim
274	98	Horseshoes, homoclinic connections and global chaos in current-mode controlled DC/DC converters	claim
275	98	Integrated blind electronic equalizer for fiber dispersion compensation	claim
276	98	An ultrasonic filterbank with spiking neurons	claim
277	97	Two-level decoupled Hamming network for associative memory under noisy environment	claim
278	96	Stereo video coding system with hybrid coding based on joint prediction scheme	claim
279	96	Synthesis of MITE log-domain filters with unique operating points	claim
280	95	Area, power, and pin efficient bus transceiver using multi-bit-differential signaling	claim
281	91	Synchronization: a fundamental phenomenon in complex dynamical networks	claim

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