ISVLSI 2006 - PDF Preprint Papers

ISVLSI 2006 IEEE Computer Society Annual Symposium on VLSI

Teaser Browsing | Click Here

Title Browsing | Click Here

Wall of Fame | Most Viewed ISVLSI-2006 Paper

click to vote

ISVLSI
2006
IEEE

150views VLSI» more ISVLSI 2006»

Design and Analysis of a Low Power VLIW DSP Core

13 years 10 months ago

Download www.ece.cmu.edu

Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...

Chan-Hao Chang, Diana Marculescu

claim paper

Read More »

Disclaimer and Copyright Notice

Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.

Id	Views	Title	Status

1	150	Design and Analysis of a Low Power VLIW DSP Core	claim
2	149	Defect-Aware Design Paradigm for Reconfigurable Architectures	claim
3	137	Low Power Layered Space-Time Channel Detector Architecture for MIMO Systems	claim
4	129	Dependability Analysis of Nano-scale FinFET circuits	claim
5	129	Connection-oriented Multicasting in Wormhole-switched Networks on Chip	claim
6	126	QUKU: A Two-Level Reconfigurable Architecture	claim
7	115	Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems	claim
8	115	The Design of Analog Front-End Circuitry for 1X HD-DVD PRML Read Channel	claim
9	114	A Low Power Lookup Technique for Multi-Hashing Network Applications	claim
10	112	Multiprocessor Systems-on-Chips	claim
11	106	Self-Timed Thermally-Aware Circuits	claim
12	105	Floorplanning Based on Particle Swarm Optimization	claim
13	104	Adaptive Signal Processing in Mixed-Signal VLSI with Anti-Hebbian Learning	claim
14	101	Nanowire Addressing in the Face of Uncertainty	claim
15	95	A Virtual Channel Network-on-Chip for GT and BE traffic	claim
16	95	PLAs in Quantum-dot Cellular Automata	claim
17	89	System Exploration of SystemC Designs	claim
18	88	Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks	claim
19	85	Variation Aware Placement for FPGAs	claim
20	82	Reliability-Aware SOC Voltage Islands Partition and Floorplan	claim
21	82	Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors	claim
22	77	A Robust Synchronizer	claim
23	60	A new Multilevel Hierarchical MFPGA and its suitable configuration tools	claim

Sciweavers

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers