ITC 1997 - PDF Preprint Papers

ITC 1997 International Test Conference

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ITC
1997
IEEE

129views Hardware» more ITC 1997»

On Using Machine Learning for Logic BIST

13 years 8 months ago

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This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...

Christophe Fagot, Patrick Girard, Christian Landra...

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Id	Views	Title	Status

1	129	On Using Machine Learning for Logic BIST	claim
2	123	Modifying User-Defined Logic for Test Access to Embedded Cores	claim
3	121	BIST-Based Diagnostics of FPGA Logic Blocks	claim
4	119	Testability Analysis and ATPG on Behavioral RT-Level VHDL	claim
5	107	Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique	claim
6	107	On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops	claim
7	100	Signal Generation Using Periodic Single-and Multi-Bit Sigma-Delta Modulated Streams	claim
8	94	Identification of Defective CMOS Devices Using Correlation and Regression Analysis of Frequency Domain Transient Signal Data	claim
9	93	Fault Diagnosis in Scan-Based BIST	claim
10	92	A Novel Functional Test Generation Method for Processors Using Commercial ATPG	claim
11	92	Capacitive Leadframe Testing	claim
12	90	Bridging Fault Diagnosis in the Absence of Physical Information	claim
13	90	So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment	claim
14	80	Scan Synthesis for One-Hot Signals	claim
15	75	An Efficient Scheme to Diagnose Scan Chains	claim
16	73	A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems	claim
17	60	Current Signatures: Application	claim
18	60	Using BIST Control for Pattern Generation	claim

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