PEPM   2009 ACM/SIGPLAN Workshop Partial Evaluation and Semantics-Based Program Manipulation
Wall of Fame | Most Viewed PEPM-2009 Paper
11 years 10 months ago
Static Consistency Checking for Verilog Wire Interconnects
The Verilog hardware description language has padding semantics that allow designers to write descriptions where wires of different bit widths can be interconnected. However, many ...
Cherif Salama, Gregory Malecha, Walid Taha, Jim Gr...
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