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SIPS 2007 Signal Processing Systems

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SIPS
2007
IEEE

162views Signal Processing» more SIPS 2007»

Exit Chart Aided Irregular Convolutional Code Design for Iterative Downlink SDMA Systems Using Imperfect Channel State Informati

13 years 10 months ago

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We analyze a precoded and iteratively detected downlink multiuser system employing imperfect Spatio-Temporal Channel Impulse Response at the Transmitters (ST-CIRT) with the aid of...

Chun-Yi Wei, Jin Wang, Lajos Hanzo

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Id	Views	Title	Status

1	162	Exit Chart Aided Irregular Convolutional Code Design for Iterative Downlink SDMA Systems Using Imperfect Channel State Information	claim
2	158	Multilevel Linc System Design for Power Efficiency Enhancement
3	158	Embedded Reconfigurable Solution for OFDM Detection Over Fast Fading Radio Channels	claim
4	154	Equalization and Interference Cancellation with MIMO THP for 10GBASE-T	claim
5	150	A Fast Mode Decision Algorithm for H.264/AVC Intra Prediction	claim
6	149	SVD-Aided, Iteratively Detected Spatial Division Multiplexing Using Long-Range Channel Prediction	claim
7	148	Layered Steered Space-Time Codes Using Iterative Detection	claim
8	148	An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding	claim
9	141	MIMO Detector Based on Viterbi Algorithm	claim
10	137	Design and Analysis of LDPC Decoders for Software Defined Radio	claim
11	133	Systematic Luby Transform Codes and Their Soft Decoding	claim
12	130	Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency	claim
13	123	Luby Transform Coding Aided Iterative Detection for Downlink SDMA Systems	claim
14	118	Optimal Data Mapping for Motion Compensation in H.264 Video Decoding	claim
15	113	Montgomery Modular Multiplication Algorithm on Multi-Core Systems	claim
16	101	Peak-to-Average Power Ratio Reduction in an FDM Broadcast System	claim
17	96	A New Video Compression Scheme Combining Conditional Replenishment and Address Event Representation	claim
18	94	Low-Overhead Run-Time Scheduling for Fine-Grained Acceleration of Signal Processing Systems	claim
19	90	Sensitivity of Time-Division Multiplexing Parallel A/D Converters to Analog Imperfection	claim
20	89	Sphere Decoding for Multiprocessor Architectures	claim
21	88	Robust Region-of-Interest Scalable Coding with Leaky Prediction in H.264/AVC	claim
22	85	Rapid Abstract Control Model for Signal Processing Implementation	claim
23	77	Iteratively Decoded Irregular Variable Length Coding and Trellis Coded Modulation	claim
24	76	Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations	claim

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