TCAD 2002 - PDF Preprint Papers

TCAD 2002

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TCAD
2002

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Static power modeling of 32-bit microprocessors

13 years 4 months ago

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The paper presents a novel strategy aimed at modelling instruction energy consumption of 32-bits microprocessors. Differently from former approaches, the proposed instruction-level...

Carlo Brandolese, Fabio Salice, William Fornaciari...

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Id	Views	Title	Status

1	158	Static power modeling of 32-bit microprocessors	claim
2	146	Static scheduling of multidomain circuits for fast functional verification	claim
3	145	Automatic generation of synthetic sequential benchmark circuits	claim
4	139	Digital filter synthesis based on an algorithm to generate all minimal signed digit representations	claim
5	137	Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicoupled transmission line system	claim
6	135	Area fill synthesis for uniform layout density	claim
7	134	Testing and diagnosis of interconnect faults in cluster-based FPGA architectures	claim
8	134	DS-LFSR: a BIST TPG for low switching activity	claim
9	129	Analytical approach to layout generation of datapath cells	claim
10	128	Preferred direction Steiner trees	claim
11	123	3-D Thermal-ADI: a linear-time chip level transient thermal simulator	claim
12	121	Robust Boolean reasoning for equivalence checking and functional property verification	claim
13	118	Application-specific clustered VLIW datapaths: early exploration on a parameterized design space	claim
14	115	Analytical models for crosstalk excitation and propagation in VLSI circuits	claim
15	110	A constructive genetic algorithm for gate matrix layout problems	claim
16	107	Value-sensitive automatic code specialization for embedded software	claim
17	106	Design of hierarchical cellular automata for on-chip test pattern generator	claim
18	104	An instruction-level energy model for embedded VLIW architectures	claim
19	104	A framework for testing special-purpose memories	claim
20	99	Analysis of on-chip inductance effects for distributed RLC interconnects	claim
21	98	An Esterel compiler for large control-dominated systems	claim
22	98	Reporting of standard cell placement results	claim
23	93	Hierarchical buffered routing tree generation	claim
24	92	Design of reconfigurable composite microsystems based on hardware/software codesign principles	claim
25	91	Retiming and clock scheduling for digital circuit optimization	claim
26	89	Publicly detectable watermarking for intellectual property authentication in VLSI design	claim
27	88	Estimating routing congestion using probabilistic analysis	claim
28	86	Platune: a tuning framework for system-on-a-chip platforms	claim
29	85	Architectural energy optimization by bus splitting	claim
30	82	Comments on "Filling algorithms and analyses for layout density control"	claim
31	79	An automorphic approach to verification pattern generation for SoC design verification using port-order fault model	claim
32	77	Fast and exact transistor sizing based on iterative relaxation	claim
33	73	A timing-constrained simultaneous global routing algorithm	claim
34	73	System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints	claim
35	72	Wire width planning for interconnect performance optimization	claim
36	64	Direct synthesis of timed circuits from free-choice STGs	claim

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