Sciweavers

VLSI   2005 VLSI Engineering: Beyond Software Engineering
Wall of Fame | Most Viewed VLSI-2005 Paper
VLSI
2005
Springer
13 years 9 months ago
Pareto Points in SRAM Design Using the Sleepy Stack Approach
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption a...
Jun-Cheol Park, Vincent John Mooney III
Disclaimer and Copyright Notice
Sciweavers respects the rights of all copyright holders and in this regard, authors are only allowed to share a link to their preprint paper on their own website. Every contribution is associated with a desciptive image. It is the sole responsibility of the authors to ensure that their posted image is not copyright infringing. This service is compliant with IEEE copyright.
IdReadViewsTitleStatus
1Download preprint from source132
2Download preprint from source127
3Download preprint from source108
4Download preprint from source95