FPGA Implementations of the ICEBERG Block Cipher

13 years 10 months ago

Download www.dice.ucl.ac.be

— This paper presents FPGA (Field Programmable Gate Array) implementations of ICEBERG, a block cipher designed for reconﬁgurable hardware implementations and presented at FSE 2004. All its components are involutional and allow very efﬁcient combinations of encryption/decryption. The implementations proposed also allow changing the key and Encrypt/Decrypt (E/D) mode for every plaintext, without any performance loss. In comparison with other recent block ciphers, the implementation results of ICEBERG show a signiﬁcant improvement of hardware efﬁciency. Moreover, the key and E/D agility allows considering new encryption modes to counteract certain side-channel attacks.

François-Xavier Standaert, Gilles Piret, Ga

Real-time Traffic

Block Ciphers | Field Programmable Gate Array | Information Technology | ITCC 2005 | Reconﬁgurable Hardware Implementations |

claim paper

» ICEBERG An Involutional Cipher Efficient for Block Encryption in Reconfigurable Hardware

» An FPGA implementation and performance evaluation of the Serpent block cipher

» 64bit Block ciphers hardware implementations and comparison analysis

» High Performance Implementation of a Public Key Block Cipher MQQ for FPGA Platforms

» A RAMbased FPGA implementation of the 64bit MISTY1 block cipher

» Exploring AreaDelay Tradeoffs in an AES FPGA Implementation

» FPGA Implementations of the RC6 Block Cipher

» Architectures and FPGA Implementations of the 64Bit MISTY1 Block Cipher

Post Info
More Details (n/a)

Added	25 Jun 2010
Updated	25 Jun 2010
Type	Conference
Year	2005
Where	ITCC
Authors	François-Xavier Standaert, Gilles Piret, Gaël Rouvroy, Jean-Jacques Quisquater

Comments (0)

Sciweavers

FPGA Implementations of the ICEBERG Block Cipher

Block Ciphers | Field Programmable Gate Array | Information Technology | ITCC 2005 | Reconﬁgurable Hardware Implementations |

Explore & Download

Productivity Tools

Document Tools

Image Tools

Sciweavers