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DATE
2010
IEEE

An evaluation of a slice fault aware tool chain

13 years 8 months ago
An evaluation of a slice fault aware tool chain
Abstract—As FPGA sizes and densities grow, their manufacturing yields decrease. This work looks toward reclaiming some of this lost yield. Several previous works have suggested fault aware CAD tools for intelligently routing around faults. In this work we evaluate such an approach quantitatively with respect to some standard benchmarks. We also quantify the trade-offs between performance and fault tolerance in such a method. Leveraging existing CAD tools, we show up to 30% of slices being faulty can be tolerated. Such approaches could potentially allow manufacturers to sell larger chips with manufacturing faults as smaller chips using a nomenclature that appropriately captures the reduction in logic resources.
Adwait Gupte, Phillip Jones
Added 10 Jul 2010
Updated 10 Jul 2010
Type Conference
Year 2010
Where DATE
Authors Adwait Gupte, Phillip Jones
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