Enhancing debugging of multiple missing control errors in reversible logic

Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising direction so that several methods for synthesis, verification, and testing of reversible circuits have already been proposed. However, also methods for debugging, i.e., to determine error candidates in case of a failed verification, are required to complete the design flow. Even if first approaches have already been proposed, debugging of reversible circuits still is in the beginning. In this paper, we present an alternative method to automatically debug reversible circuits. We thereby focus on missing control errors – an established error model in the design of reversible circuits. A new notion of an error candidate is proposed that relies on the observation of a necessary condition for error locations in reversible circuits. Using this notion, a set of error candidates is obtained that differs from the error...

• Type: Conference
• Year: 2010
• Where: GLVLSI
• Authors: Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler
• Keywords: Error Candidates, GLVLSI 2010, Reversible Circuits, Reversible Logic, VLSI