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FPL
2009
Springer

Using 3D integration technology to realize multi-context FPGAs

13 years 8 months ago
Using 3D integration technology to realize multi-context FPGAs
This paper advocates the use of 3D integration technology to stack a DRAM on top of an FPGA. The DRAM will store future FPGA contexts. A configuration is read from the DRAM into a latch array on the DRAM layer while the FPGA executes; the new configuration is loaded from the latch array into the FPGA in 60ns (5 cycles). The latency between reconfigurations, 8.42μs, is dominated by the time to read data from the DRAM into the latch array. We estimate that the DRAM can cache 289 FPGA contexts.
Alessandro Cevrero, Panagiotis Athanasopoulos, Had
Added 24 Jul 2010
Updated 24 Jul 2010
Type Conference
Year 2009
Where FPL
Authors Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne
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