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DATE
2000
IEEE

An on Chip ADC Test Structure

13 years 8 months ago
An on Chip ADC Test Structure
In this paper, a new built-in self-test structure to test the static specifications of analog to digital converters (ADCs) is presented. A ramp signal generated by an integrator serves as a test input signal. A specific range of this signal is divided into ¾Ò·½ segments, with each segment corresponding to one output combination of an n+1-bit counter, where n is the number of bits of the ADCs under test. The testing process is done with digital data processing by comparing the outputs of ADCs under test with the outputs of the n+1bit counter. Simple structure, low area overhead, and high speed are the advantages of the proposed test structure.
Yun-Che Wen, Kuen-Jong Lee
Added 30 Jul 2010
Updated 30 Jul 2010
Type Conference
Year 2000
Where DATE
Authors Yun-Che Wen, Kuen-Jong Lee
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