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ASPLOS
2000
ACM

FLASH vs. (Simulated) FLASH: Closing the Simulation Loop

13 years 8 months ago
FLASH vs. (Simulated) FLASH: Closing the Simulation Loop
Simulation is the primary method for evaluating computer systems during all phases of the design process. One significant problem with simulation is that it rarely models the system exactly, and quantifying the resulting simulator error can be difficult. More importantly, architects often assume without proof that although their simulator may make inaccurate absolute performance predictions, it will still accurately predict architectural trends. This paper studies the source and magnitude of error in a range of architectural simulators by comparing the simulated execution time of several applications and microbenchmarks to their execution time on the actual hardware being modeled. The existence of a hardware gold standard allows us to find, quantify, and fix simulator inaccuracies. We then use the simulators to predict architectural trends and analyze the sensitivity of the results to the simulator configuration. We find that most of our simulators predict trends accurately, as lo...
Jeff Gibson, Robert Kunz, David Ofelt, Mark Heinri
Added 01 Aug 2010
Updated 01 Aug 2010
Type Conference
Year 2000
Where ASPLOS
Authors Jeff Gibson, Robert Kunz, David Ofelt, Mark Heinrich
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