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DAC
1999
ACM

Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages

13 years 8 months ago
Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages
Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply voltage for gates off the critical path it is possible to dramatically reduce power consumption in CMOS VLSI circuits without performance degradation. Interfacing gates operating under multiple supply voltages, however, requires the use of level converters, which makes the problem modeling difficult. In this paper we develop a formal model and develop an efficient heuristic for addressing the use of two supply voltages for low power CMOS VLSI circuits without performance degradation. Power consumption savings up to 25% over and above the best known existing heuristics are demonstrated for combinational circuits in the ISCAS85 benchmark suite.
Vijay Sundararajan, Keshab K. Parhi
Added 02 Aug 2010
Updated 02 Aug 2010
Type Conference
Year 1999
Where DAC
Authors Vijay Sundararajan, Keshab K. Parhi
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