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DATE
1999
IEEE

Glitch Power Minimization by Gate Freezing

13 years 8 months ago
Glitch Power Minimization by Gate Freezing
This paper presents a technique for glitch power minimization in combinational circuits. The total number of glitches is reduced by replacing some existing gates with functionally equivalent ones called F-Gates that can be frozen" by asserting a control signal. A frozen gate cannot propagate glitches to its output. An important feature of the proposed method is that it can be applied in-place directly to layout-level descriptions; therefore, it guarantees very predictable results and minimizes the impact of the transformation on circuit size and speed.
Luca Benini, Giovanni De Micheli, Alberto Macii, E
Added 02 Aug 2010
Updated 02 Aug 2010
Type Conference
Year 1999
Where DATE
Authors Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
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