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7

ISCAS
1999
IEEE

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Fast FPGA-based pipelined digit-serial/parallel multipliers

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Fast FPGA-based pipelined digit-serial/parallel multipliers

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Javier Valls, T. Sansaloni, M. M. Peiro, Eduardo I

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Added	03 Aug 2010
Updated	03 Aug 2010
Type	Conference
Year	1999
Where	ISCAS
Authors	Javier Valls, T. Sansaloni, M. M. Peiro, Eduardo I. Boemo

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