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DATE
2004
IEEE

Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors

13 years 7 months ago
Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors
This paper proposes a low-energy solution for CAMbased highly associative I-caches using a segmented wordline and a predictor-based instruction fetch mechanism. Not all instructions in a given I-cache fetch are used due to branches. The proposed predictor determines which instructions in a cache access will be used and does not fetch any other instructions. Results show an average I-cache energy savings of 44% over the baseline case and 6% over the segmented case with no negative impact on performance.
Juan L. Aragón, Dan Nicolaescu, Alexander V
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2004
Where DATE
Authors Juan L. Aragón, Dan Nicolaescu, Alexander V. Veidenbaum, Ana-Maria Badulescu
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