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FPL
2006
Springer

From Equation to VHDL: Using Rewriting Logic for Automated Function Generation

13 years 7 months ago
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation
This paper presents a novel tool flow combining rewriting logic with hardware synthesis. It enables the automated generation of synthesizable VHDL code from mathematical equations and the quick generation of functionally equivalent alternative implementations. The simple but powerful semantics of rewriting logic provide a natural mechanism for manipulating algebraic expressions, using a high-level action which is afterwards automatically converted er levels of abstraction. The design flow is validated by generating polynomial approximations for arbitrary continuous functions. The polynomial generation process is completely parameterized regarding polynomial degree, number representation parameters, word width and polynomial evaluation approaches. Different functionally equivalent implementations for the resulting polynomial approximations were generated and synthesized for a Virtex4 device.
Carlos Morra, M. Sackmann, Sunil Shukla, Jürg
Added 22 Aug 2010
Updated 22 Aug 2010
Type Conference
Year 2006
Where FPL
Authors Carlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker, Reiner W. Hartenstein
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