Leading Zero Anticipation and Detection-A Comparison of Methods

Design of the leading zero anticipator ( L a ) or detector (LZD) is pivotal to the normalization of results for addition and fused multiplication-addition in highperjormance floating point processors. This paper formalizes the analysis and describes some alternative organizations and implementationsfrom the known art. It shows how choices made in the design are ofen dependent on the overall design of the addition unit, on how subtraction is handled when the exponents are the same, and on how it detects and correctsfor the possible one-bit error of the 15%.

• Type: Conference
• Year: 2001
• Where: ARITH
• Authors: Martin S. Schmookler, Kevin J. Nowka
• Keywords: Alternative Organizations, Applied Computing, ARITH 2001, Leading Zero, Possible One-bit Error