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11

ATS
2001
IEEE

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Framework of Timed Trace Theoretic Verification Revisited

13 years 8 months ago

Framework of Timed Trace Theoretic Verification Revisited

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This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarchical verification of timed circuits and systems. Finally, we relate our framework to those previously proposed for timing verification.

Bin Zhou, Tomohiro Yoneda, Chris J. Myers

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ATS 2001 | Hardware | Hierarchical Verification | Timed Circuits | Trace Theoretic Verification |

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Added	23 Aug 2010
Updated	23 Aug 2010
Type	Conference
Year	2001
Where	ATS
Authors	Bin Zhou, Tomohiro Yoneda, Chris J. Myers

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