Memory Aware High-Level Synthesis for Embedded Systems

We introduce a new approach to take into account the memory architecture and the memory mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a memory mapping file to include those memory constraints in our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time. Several experiments are performed to demonstrate the efficiency of our method, and to compare GAUT with an industrial behavioral synthesis tool. We finally show how to explore, with the help of GAUT, a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area. KEYWORDS High-Level Synthesis, memory, embedded systems.

• Type: Journal
• Year: 2006
• Where: CORR
• Authors: Gwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin
• Keywords: CORR 2006, Education, Memory Constraint Graph, Memory Constraints, Memory Mapping