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CAI
2004
Springer

An Evolvable Combinational Unit for FPGAs

13 years 3 months ago
An Evolvable Combinational Unit for FPGAs
A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evolutionary algorithm was described in VHDL independently of a target platform, i.e. as a soft IP core, and realized in the COMBO6 card. In many cases the unit is able to evolve (i.e. to design) the required function automatically and autonomously, in a few seconds, only on the basis of interactions with an environment. A number of circuits were successfully evolved directly in the FPGA, in particular, 3-bit multipliers, adders, multiplexers and parity encoders. The evolvable unit was also tested in a simulated dynamic environment and used to design various circuits specified by randomly generated truth tables.
Lukás Sekanina, Stepan Friedl
Added 16 Dec 2010
Updated 16 Dec 2010
Type Journal
Year 2004
Where CAI
Authors Lukás Sekanina, Stepan Friedl
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