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ICCAD
2010
IEEE

Synthesis of an efficient controlling structure for post-silicon clock skew minimization

13 years 1 months ago
Synthesis of an efficient controlling structure for post-silicon clock skew minimization
Clock skew minimization has been an important design constraint. However, due to the complexity of Process, Voltage, and Temperature (PVT) variations, the minimization of clock skew has faced a great challenge. To overcome the influence of PVT variations, several previous works proposed Post Silicon Tuning (PST) architecture to dynamically balance the skew of a clock tree. In the PST architecture, there are two main components: Adjustable Delay Buffer (ADB) and Phase Detector (PD). Most previous works focus on determining good positions of ADBs in a PST design. In this paper, we first show that which pairs of FFs are connected to PDs, called PD structure, also greatly influence the complexity of hardware control for a PST design. Without careful planning of a PD structure, we need large number of control signals to adjust the delays of ADBs. In addition, we also show that a PD structure may influence the accuracy of the clock skew. Among possible connection structures, this paper prop...
Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih
Added 11 Feb 2011
Updated 11 Feb 2011
Type Journal
Year 2010
Where ICCAD
Authors Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih-Chieh Chang
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